Source switched split LNA

Patent metadata

Field	Value
Publication number	US-11005425-B2
Application number	US-201916677477-A
Country	US
Kind code	B2
Filing date	Nov 7, 2019
Priority date	Jul 15, 2016
Publication date	May 11, 2021
Grant date	May 11, 2021

Abstract

A receiver front end capable of receiving and processing intraband non-contiguous carrier aggregate (CA) signals using multiple low noise amplifiers (LNAs) is disclosed herein. A cascode having a “common source” configured input FET and a “common gate” configured output FET can be turned on or off using the gate of the output FET. A first switch is provided that allows a connection to be either established or broken between the source terminal of the input FET of each LNA. Further switches used for switching degeneration inductors, gate capacitors and gate to ground caps for each legs can be used to further improve the matching performance of the invention.

First claim

What is claimed is:

1. An amplifier including:
(a) a plurality of low noise amplifiers (LNA), each including an input transistor and an output transistor;
(b) at least one source switch connecting a source terminal of the input transistor of at least a first of the LNAs and a source terminal of the input transistor of at least a second of the LNAs during a first mode of operation and disconnecting the source terminals during at least a second mode of operation;
wherein during the first mode of operation signals turn one of the LNAs on and the other LNAs off; and
wherein during the second mode of operation signals applied to turn on at least a first and second of the LNAs, wherein the first LNA has an input transistor with source terminal that is disconnected by one of the source switches from the source terminal of the input transistor of the LNAs that are on.

2. The amplifier of claim 1 , further including:
(a) a first degeneration component;
(b) a first degeneration switch coupled in series with the first degeneration component, the series combination of the first degeneration component and the first degeneration switch coupled between the source terminal of a first of the input transistors and ground.

3. The amplifier of claim 2 , further including:
(a) at least one second degeneration component;
(b) at least one second degeneration switch coupled in series with a corresponding one of the at least one second degeneration component, each series combination of the second degeneration component and the corresponding second degeneration switch coupled between the source terminal of the input transistor of a corresponding one of the plurality of LNAs and circuit ground.

4. The amplifier of claim 1 , further including
(a) a gate capacitance module, the gate capacitance module having a first and second terminal, the first terminal coupled to a gate of an associated one of the input transistors and the second terminal coupled to the source terminal of the associated input transistor;
(b) at least one additional gate capacitance module, each additional gate capacitance module having a first and second terminal, the first terminal coupled to a gate of an associated one of the input transistors and the second terminal coupled to a source terminal of the associated input transistor.

5. The amplifier of claim 4 , further including a control module having at least one switch control signal output, wherein each gate capacitance module has a switch control signal input to which a corresponding switch control signal output is coupled.

6. The amplifier of claim 4 , wherein each gate capacitance module includes a gate capacitor and a gate switch coupled in series between the first terminal and the second terminal of the gate capacitance module.

7. The amplifier of claim 6 , wherein each gate switch is open when an associated input transistor is conducting and closed when the associated input transistor is not conducting.

8. The amplifier of claim 1 , further including at least one gate capacitance module, each gate capacitance module having a first and second terminal, the first terminal of the gate capacitance module coupled to a gate of an associated one of the input transistors and the second terminal of the gate capacitance module coupled to ground.

9. The amplifier of claim 8 , further including a control module having at least one switch control signal output, wherein each gate capacitance module has a switch control signal input to which a corresponding switch control signal output is coupled.

10. The amplifier of claim 8 , wherein each gate capacitance module includes a gate capacitor and a gate switch coupled in series between the first terminal and the second terminal of the gate capacitance module.

11. The amplifier of claim 10 , wherein each gate switch is open when an associated input transistor is on and closed when the associated input transistor is off.

12. The amplifier of claim 2 , further including at least one gate capacitance module, each gate capacitance module having a first and second terminal, the first terminal of each gate capacitance module coupled to a gate of an associated one of the input transistors and the second terminal of each gate capacitance module coupled to ground.

13. The amplifier of claim 2 , wherein the first degeneration component is a degeneration inductor.

14. The amplifier of claim 2 , wherein the first degeneration switch is open when the source switch to which the first degeneration switch is coupled is closed and closed when the source switch to which the first degeneration switch is coupled is open.

15. The amplifier of claim 3 , wherein the at least one second degeneration switch is open when the first degeneration switch is closed and is closed when the first degeneration switch is open.

16. The amplifier of claim 2 , further including a control module having a switch control signal output, wherein the first degeneration switch has a switch control signal input to which the switch control signal output is coupled.

17. The amplifier of claim 4 , further including:
(a) a first degeneration component;
(b) a first degeneration switch coupled in series with the first degeneration component, the series combination of the first degeneration component and first degeneration switch coupled between the source terminal of a first of the input transistors and ground.

18. The amplifier of claim 17 , wherein the first degeneration component is an inductor.

19. The amplifier of claim 17 , wherein each gate capacitance module includes a gate capacitor and a gate switch coupled in series between the first terminal and the second terminal of the gate capacitance module,
wherein the first degeneration switch is open when the source switch to which the first degeneration switch is coupled is closed and closed when the source switch to which the first degeneration switch is coupled is open and
wherein the gate switch is closed when the source switch to which the first degeneration switch is coupled is closed and open when the source switch to which the first degeneration switch is coupled is open.

20. The amplifier of claim 17 , further including a second degeneration inductor and a second degeneration switch coupled in series between the source terminal of a second input transistor and ground,
wherein each gate capacitance module includes a gate capacitor and a gate switch coupled in series between the first terminal and the second terminal of the gate capacitance module,
wherein the first degeneration switch is open when the source switch to which the first degeneration switch is coupled is closed and closed when the source switch to which the first degeneration switch is coupled is open,
wherein the gate switch is closed when the source switch to which the first degeneration switch is coupled is closed and open when the source switch to which the first degeneration switch is coupled is open and
wherein the second degeneration switch is closed when the first degeneration switch is open and open with the first degeneration switch is closed.

Assignees

• Psemi Corp

Inventors

• Ayranci Emre
• Sanner Miles

Classifications

• H03F1/086 Primary

  with FET's · CPC title

• H03F2200/111

  the amplifier being a dual or triple band amplifier, e.g. 900 and 1800 MHz, e.g. switched or not switched, simultaneously or not · CPC title

• H03F2200/411

  the output amplifying stage of an amplifier comprising two power stages · CPC title

• H03F2200/225

  the input circuit of an amplifying stage comprising an LC-network · CPC title

• H03F2203/7206

  the gated amplifier being switched on or off by a switch in the bias circuit of the amplifier controlling a bias voltage in the amplifier · CPC title