Circuits and methods related to low-noise amplifiers having improved linearity

Patent metadata

Field	Value
Publication number	US-9407215-B2
Application number	US-201414274663-A
Country	US
Kind code	B2
Filing date	May 9, 2014
Priority date	May 10, 2013
Publication date	Aug 2, 2016
Grant date	Aug 2, 2016

Abstract

Disclosed are circuits and methods related to low-noise amplifiers (LNAs) having improved linearity. In some embodiments, a radio-frequency (RF) amplifier circuit can include a first amplifying transistor configured to amplify an RF signal. The RF amplifier circuit can further include a switchable inductance circuit that couples the first amplifying transistor to a signal ground. The switchable inductance circuit can be configured to be capable of providing at least two different inductance values that yield different linearity levels for the RF amplifier circuit. A high linearity performance can be obtained with a higher inductance and a lower bias voltage, thereby reducing power consumption of the RF amplifier. Examples of methods and devices related to such an RF amplifier circuit are disclosed.

First claim

What is claimed is:

1. A radio-frequency (RF) amplifier circuit comprising:
a first amplifying transistor configured to amplify an RF signal;
a switchable inductance circuit that couples the first amplifying transistor to a signal ground, the switchable inductance circuit configured to be capable of having a selected one of a plurality of different inductance values that yield different linearity levels for the RF amplifier circuit; and
a processing device configured to determine a linearity mode of the RF amplifier circuit and to control the switchable inductance circuit to have the selected one of the plurality of different inductance values based on the determined linearity mode.

2. The circuit of claim 1 wherein the first amplifying transistor includes a source, a drain and a gate, the first amplifying transistor configured to receive the RF signal at the gate and output the amplified RF signal at the drain.

3. The circuit of claim 2 wherein the switchable inductance circuit couples the source of the first amplifying transistor to the signal ground.

4. The circuit of claim 1 wherein the RF amplifier circuit is a low-noise amplifier (LNA) circuit.

5. The circuit of claim 1 wherein the switchable inductance circuit includes a first inductance connected electrically parallel with a switch, the processing device being configured to set the switch in a closed state or an open state to control the switchable inductance circuit to have a first one of the plurality of different inductance values or a second one of the plurality of different inductance values based on the determined linearity mode.

6. The circuit of claim 5 further comprising a second inductance connected in series with the switchable inductance circuit such that an overall inductance between the source of the first transistor and the signal ground is approximately equal to the second inductance when the switch is in the closed state and approximately equal to a sum of the first and second inductances when the switch is in the open state.

7. The circuit of claim 6 wherein the first inductance and the second inductance are selected so that the RF amplifier circuit operates in a normal linearity mode when the switch is in the closed state and a high linearity mode when the switch is in the open state.

8. The circuit of claim 1 further comprising a bias circuit, the bias circuit including a variable current source configured to provide a bias voltage to the first amplifying transistor.

9. The circuit of claim 8 wherein the bias voltage has a first magnitude when the RF amplifier circuit operates in a normal linearity mode and a second magnitude when the RF amplifier circuit operates in a high linearity mode.

10. The circuit of claim 9 wherein the second magnitude of the bias voltage is lower than the first magnitude of the bias voltage.

11. The circuit of claim 10 wherein the RF amplifier circuit consumes less power in the high linearity mode than in the normal linearity mode due to the second magnitude of the bias voltage being lower than the first magnitude of the bias voltage.

12. The circuit of claim 3 further comprising a second amplifying transistor coupled to the drain of the first transistor, the first amplifying transistor and the second amplifying transistors being connected and operated in a cascode configuration.

13. The circuit of claim 12 wherein each of the first amplifying transistor and the second amplifying transistor is a field-effect transistor (FET).

14. A method for operating a radio-frequency (RF) amplifier circuit, the method comprising:
providing an RF signal to a transistor of the RF amplifier circuit to amplify the RF signal;
determining a linearity mode of the RF amplifier circuit; and
performing a switching operation based on the determined linearity mode that results in an inductance to change among a plurality of different inductance values between the transistor and a signal ground, the plurality of different inductance values yielding different linearity levels for the RF amplifier circuit.

15. The method of claim 14 further comprising adjusting a bias voltage provided to the transistor to yield a selected bias voltage for each of the plurality of different inductance values.

16. The method of claim 15 wherein a higher linearity level corresponds to an increased inductance value of the plurality of different inductance values and a decreased bias voltage of the selected bias voltages.

17. The method of claim 16 wherein the increased inductance value and the decreased bias voltage results in the RF amplifier circuit consuming less power at the higher linearity level.

18. A radio-frequency (RF) module, comprising:
a packaging substrate configured to receive a plurality of components;
a low-noise amplifier (LNA) implemented on a die, the die mounted on the packaging substrate, the LNA including a transistor configured to amplify an RF signal;
a switchable inductance circuit that couples the transistor to a signal ground, the switchable inductance circuit configured to be capable of having a selected one of a plurality of different inductance values that yield different linearity levels for the LNA; and
a processing device configured to determine a linearity mode of the LNA and to control the switchable inductance circuit to have the selected one of the plurality of different inductance values based on the determined linearity mode.

19. The module of claim 18 wherein at least a portion of the switchable inductance circuit is also implemented on the die.

20. The module of claim 18 wherein the die includes a silicon-on-insulator (SOI) substrate.

Assignees

• Skyworks Solutions Inc

Inventors

• Gill Bharatjeet Singh

Classifications

• H03F3/195 Primary

  in integrated circuits · CPC title

• H03F3/245

  with semiconductor devices only · CPC title

• H03F3/193

  with field-effect devices (H03F3/195 takes precedence) · CPC title

• H03F1/3205

  in field-effect transistor amplifiers · CPC title

• H03F2200/108

  A coil being added in the drain circuit of a FET amplifier stage, e.g. for noise reducing purposes · CPC title