Hybrid backside thermal structures for enhanced ic packages

US12482779B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-12482779-B2
Application numberUS-202418593775-A
CountryUS
Kind codeB2
Filing dateMar 1, 2024
Priority dateFeb 7, 2020
Publication dateNov 25, 2025
Grant dateNov 25, 2025

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

An integrated circuit (IC) die structure comprises a substrate material comprising silicon. Integrated circuitry is over a first side of the substrate material. A composite layer is in direct contact with a second side of the substrate material. The second side is opposite the first side. The composite layer comprises a first constituent material associated with a first linear coefficient of thermal expansion (CTE), and a first thermal conductivity exceeding that of the substrate. The composite layer also comprises a second constituent material associated with a second CTE that is lower than the first, and a second thermal conductivity exceeding that of the substrate.

First claim

Opening claim text (preview).

We claim: 1 . An apparatus, comprising: an integrated circuit (IC) die comprising integrated circuitry over a first side of a material layer comprising silicon, and a second side of the IC die opposite the first side of the material layer; and a composite layer on the second side of the IC die, wherein the composite layer comprises: a first constituent material having a first linear coefficient of thermal expansion (CTE) and a first thermal conductivity, the first thermal conductivity exceeding that of the material layer; and a second constituent material having a second CTE, the second CTE lower than the first CTE by at least 5 ppm/K, and a second thermal conductivity exceeding that of the material layer, wherein the composite layer comprises particles of one of the first or second constituent materials embedded within another of the first or second constituent materials. 2 . The apparatus of claim 1 , wherein the first thermal conductivity is at least 200 W/m-K, the second thermal conductivity is at least 200 W/m-K, the first CTE is over 10 ppm/K, and the second CTE is less than 5 ppm/K. 3 . The apparatus of claim 1 , wherein the composite layer comprises a plurality of lamellae, individual ones of the lamellae comprising ones of the particles of the first or second constituent material clad by the other of the first or second constituent materials. 4 . The apparatus of claim 1 , wherein the particles have a diameter greater than 1 μm. 5 . The apparatus of claim 1 , wherein the composite layer has a first thickness over a first region of the material layer and, over a second region of the material layer, the composite layer is absent or has a second thickness significantly less than the first thickness. 6 . The apparatus of claim 1 , wherein the IC die comprises at least one second material layer between the composite layer and the material layer, the at least one second material layer comprising one or more of platinum, palladium, nickel, vanadium, tantalum, titanium, tungsten, chromium, copper, gold, silver, indium, tin, aluminum, nitrogen, or oxygen. 7 . The apparatus of claim 1 , further comprising: a network interface or a display device coupled to the IC die. 8 . An apparatus, comprising: an integrated circuit (IC) die comprising integrated circuitry over a first side of a material layer comprising silicon, and a second side of the IC die opposite the first side of the material layer; and a composite layer on the second side of the IC die, wherein the composite layer comprises: a first constituent material having a first linear coefficient of thermal expansion (CTE) and a first thermal conductivity, the first thermal conductivity exceeding that of the material layer; and a second constituent material having a second CTE, the second CTE lower than the first CTE by at least 5 ppm/K, and a second thermal conductivity exceeding that of the material layer, wherein the composite layer comprises particles of one of the second constituent material embedded within a matrix of the first constituent material. 9 . The apparatus of claim 8 , wherein the first thermal conductivity is at least 200 W/m-K, the second thermal conductivity is at least 200 W/m-K, the first CTE is over 10 ppm/K, and the second CTE is less than 5 ppm/K. 10 . The apparatus of claim 8 , wherein the first constituent material is a metal and the second constituent material is a non-metal. 11 . The apparatus of claim 8 , wherein the first constituent material comprises at least one of copper, silver, or aluminum, and wherein the second constituent material comprises at least one of aluminum nitride, silicon carbide, boron arsenide, or diamond. 12 . The apparatus of claim 8 , wherein the first constituent material has a higher ductility than the second constituent material. 13 . The apparatus of claim 8 , wherein the IC die comprises at least one second material layer between the composite layer and the material layer, the at least one second material layer comprising one or more of platinum, palladium, nickel, vanadium, tantalum, titanium, tungsten, chromium, copper, gold, silver, indium, tin, aluminum, nitrogen, or oxygen. 14 . The apparatus of claim 8 , further comprising: a network interface or a display device coupled to the IC die. 15 . An apparatus, comprising: an integrated circuit (IC) die comprising integrated circuitry over a first side of a material layer comprising silicon, and a second side of the IC die opposite the first side of the material layer; and a composite layer on the second side of the IC die, wherein the composite layer comprises: a first constituent material having a first linear coefficient of thermal expansion (CTE) and a first thermal conductivity, the first thermal conductivity exceeding that of the material layer; and a second constituent material having a second CTE, the second CTE lower than the first CTE by at least 5 ppm/K, and a second thermal conductivity exceeding that of the material layer, wherein the composite layer comprises alternating layers of the first constituent material and the second constituent material. 16 . The apparatus of claim 15 , wherein the first thermal conductivity is at least 200 W/m-K, the second thermal conductivity is at least 200 W/m-K, the first CTE is over 10 ppm/K, and the second CTE is less than 5 ppm/K. 17 . The apparatus of claim 15 , wherein the first constituent material is a metal and the second constituent material is a non-metal. 18 . The apparatus of claim 15 , wherein the first constituent material comprises at least one of copper, silver, or aluminum, and wherein the second constituent material comprises at least one of aluminum nitride, silicon carbide, boron arsenide, or diamond. 19 . The apparatus of claim 15 , wherein the IC die comprises at least one second material layer between the composite layer and the material layer, the at least one second material layer comprising one or more of platinum, palladium, nickel, vanadium, tantalum, titanium, tungsten, chromium, copper, gold, silver, indium, tin, aluminum, nitrogen, or oxygen. 20 . The apparatus of claim 15 , further comprising: a network interface or a display device coupled to the IC die.

Assignees

Inventors

Classifications

  • not comprising solid metals or solid metalloids, e.g. ceramics · CPC title

  • comprising metals or metalloids, e.g. solders · CPC title

  • Die-attach connectors having a filler embedded in a matrix · CPC title

  • characterised by their shape or disposition · CPC title

  • Encapsulations, e.g. protective coatings · CPC title

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What does patent US12482779B2 cover?
An integrated circuit (IC) die structure comprises a substrate material comprising silicon. Integrated circuitry is over a first side of the substrate material. A composite layer is in direct contact with a second side of the substrate material. The second side is opposite the first side. The composite layer comprises a first constituent material associated with a first linear coefficient of th…
Who is the assignee on this patent?
Intel Corp
What technology area does this patent fall under?
Primary CPC classification H10W72/30. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Nov 25 2025 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 2 related publications on this page (citations in our corpus or others sharing the same primary CPC).