Hybrid backside thermal structures for enhanced IC packages

Patent metadata

Field	Value
Publication number	US-11948906-B2
Application number	US-202016785014-A
Country	US
Kind code	B2
Filing date	Feb 7, 2020
Priority date	Feb 7, 2020
Publication date	Apr 2, 2024
Grant date	Apr 2, 2024

Abstract

An integrated circuit (IC) die structure comprises a substrate material comprising silicon. Integrated circuitry is over a first side of the substrate material. A composite layer is in direct contact with a second side of the substrate material. The second side is opposite the first side. The composite layer comprises a first constituent material associated with a first linear coefficient of thermal expansion (CTE), and a first thermal conductivity exceeding that of the substrate. The composite layer also comprises a second constituent material associated with a second CTE that is lower than the first, and a second thermal conductivity exceeding that of the substrate.

First claim

We claim:

1. An integrated circuit (IC) die structure, comprising:
a substrate material comprising silicon;
integrated circuitry over a first side of the substrate material; and
a composite layer in direct contact with a second side of the substrate material, opposite the first side, wherein the composite layer comprises:
a first constituent material associated with a first linear coefficient of thermal expansion (CTE), and a first thermal conductivity exceeding that of the substrate material; and
a second constituent material associated with a second CTE that is lower than the first CTE by at least 5 ppm/K, and a second thermal conductivity exceeding that of the substrate material, wherein the first constituent material has a higher ductility than the second constituent material, and wherein the first constituent material is a metal and the second constituent material is a non-metal.

2. The IC die structure of claim 1 , wherein the composite layer has a thickness between 20 microns and 500 microns.

3. The IC die structure of claim 1 , wherein the first thermal conductivity is at least 200 W/m-K, the second thermal conductivity is at least 200 W/m-K, the first CTE is over 10 ppm/K, and the second CTE is less than 5 ppm/K.

4. The IC die structure of claim 1 , wherein the substrate material is associated with a third CTE that is between the first CTE and second CTE.

5. The IC die structure of claim 1 , wherein the second constituent material comprises at least one of aluminum nitride, silicon carbide, boron arsenide or diamond.

6. The IC die structure of claim 5 , wherein the first constituent material comprises at least one of copper, silver, or aluminum.

7. The IC die structure of claim 1 , wherein the composite layer comprises particles of one of the first or second constituent materials embedded within another of the first or second constituent materials.

8. The IC die structure of claim 7 , wherein the composite layer comprises particles of the second constituent material embedded within the first constituent material.

9. The IC die structure of claim 8 , wherein the composite layer comprises a plurality of lamellae, individual ones of the lamellae comprising ones of the particles of the second constituent material clad by the first constituent material.

10. The IC die structure of claim 7 , wherein the particles have a diameter greater than 1 μm.

11. The IC die structure of claim 1 , wherein the substrate material has an edge sidewall, and wherein the composite layer is absent from the edge sidewall.

12. The IC die structure of claim 1 , wherein the composite layer has a first thickness over a first region of the substrate material and, over a second region of the substrate material, the composite layer is absent or has a second thickness significantly less than the first thickness.

13. The IC die structure of claim 1 , wherein the substrate material comprises:
a monocrystalline material layer comprising silicon; and
at least one of a diffusion barrier material layer or an adhesion material layer between the composite layer and the monocrystalline material layer.

14. The IC die structure of claim 13 , wherein the diffusion barrier material layer or the adhesion material layer comprises one or more of platinum, palladium, nickel, vanadium, tantalum, titanium, tungsten, chromium, copper, gold, silver, indium, tin, aluminum, nitrogen or oxygen.

15. The IC die structure of claim 1 , further comprising:
a network interface or a display device coupled to the integrated circuitry.

16. An integrated circuit (IC) die structure, comprising:
an IC die comprising a monocrystalline material layer comprising silicon, integrated circuitry over a first side of the monocrystalline material layer, and a second side of the IC die opposite the first side of the monocrystalline material layer; and
a composite layer on the second side of the IC die, wherein the composite layer comprises:
a first constituent material having a first linear coefficient of thermal expansion (CTE) and a first thermal conductivity, the first thermal conductivity exceeding that of the monocrystalline material layer; and
a second constituent material having a second CTE, the second CTE lower than the first CTE by at least 5 ppm/K, and a second thermal conductivity exceeding that of the monocrystalline material layer.

17. The IC die structure of claim 16 , wherein the composite layer has a thickness between 20 microns and 500 microns.

18. The IC die structure of claim 16 , wherein the first constituent material is a metal and the second constituent material is a non-metal.

19. The IC die structure of claim 16 , wherein the first thermal conductivity is at least 200 W/m-K, the second thermal conductivity is at least 200 W/m-K, the first CTE is over 10 ppm/K, and the second CTE is less than 5 ppm/K.

20. The IC die structure of claim 16 , wherein the first constituent material comprises at least one of copper, silver, or aluminum, and wherein the second constituent material comprises at least one of aluminum nitride, silicon carbide, boron arsenide, or diamond.

21. The IC die structure of claim 16 , wherein the composite layer comprises particles of one of the first or second constituent materials embedded within another of the first or second constituent materials.

22. The IC die structure of claim 16 , wherein the monocrystalline material layer has an edge sidewall, and wherein the composite layer is absent from the edge sidewall.

23. The IC die structure of claim 16 , wherein the composite layer has a first thickness over a first region of IC die and, over a second region of the IC die, the composite layer is absent or has a second thickness significantly less than the first thickness.

24. The IC die structure of claim 16 , wherein the IC die comprises at least one of a diffusion barrier material layer or an adhesion material layer between the composite layer and the monocrystalline material layer, the diffusion barrier material layer or the adhesion material layer comprising one or more of platinum, palladium, nickel, vanadium, tantalum, titanium, tungsten, chromium, copper, gold, silver, indium, tin, aluminum, nitrogen or oxygen.

25. The IC die structure of claim 16 , further comprising:
a network interface or a display device coupled to the integrated circuitry.

Assignees

• Intel Corp

Inventors

• Eid Feras
• Walczyk Joe
• Tang Weihua
• Rallabandi Akhilesh
• Cartas Ayala Marco Aurelio

Classifications

• H10W72/353

  not comprising solid metals or solid metalloids, e.g. ceramics · CPC title

• H10W72/352

  comprising metals or metalloids, e.g. solders · CPC title

• H10W72/325

  Die-attach connectors having a filler embedded in a matrix · CPC title

• H10W74/10

  characterised by their shape or disposition · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title