Metal pads over TSV

Patent metadata

Field	Value
Publication number	US-12482776-B2
Application number	US-202418582312-A
Country	US
Kind code	B2
Filing date	Feb 20, 2024
Priority date	Jun 13, 2018
Publication date	Nov 25, 2025
Grant date	Nov 25, 2025

Abstract

Representative techniques and devices including process steps may be employed to mitigate the potential for delamination of bonded microelectronic substrates due to metal expansion at a bonding interface. For example, a metal pad having a larger diameter or surface area (e.g., oversized for the application) may be used when a contact pad is positioned over a TSV in one or both substrates.

First claim

What is claimed is:

1 . A method of forming a microelectronic assembly, comprising:
providing a first through substrate via (TSV) in a first substrate having a first surface; forming a first metal contact pad in the first surface electrically coupled to and aligned over the first TSV; forming a second metal contact pad in the first surface, the second metal contact pad having no TSV aligned thereunder, wherein the second metal contact pad has a different structure from the first metal contact pad to allow greater expansion of the TSV and first metal contact pad relative to the second metal contact pad; and treating the first surface, the first metal contact pad and the second metal contact pad to form a first bonding surface for direct hybrid bonding.

2 . The method of claim 1 , wherein the second metal contact pad is thicker in a dimension normal to the first bonding surface than the first metal contact pad.

3 . The method of claim 2 , wherein the second metal contact pad has a smaller surface area at the first bonding surface than the first metal contact pad.

4 . The method of claim 2 , wherein treating the first surface, the first metal contact pad and the second metal contact pad to form the first bonding surface for direct hybrid bonding comprises chemical mechanical planarization.

5 . The method of claim 1 , wherein treating the first surface, the first metal contact pad and the second metal contact pad to form the first bonding surface for hybrid direct bonding comprises recessing the first metal contact pad from a dielectric surface of the first bonding surface to a greater degree than recessing the second metal contact pad from the dielectric surface to leave the second metal contact pad thicker than the first metal contact pad.

6 . The method of claim 5 , wherein recessing the first metal contact pad from the first surface to a greater degree than recessing the second metal contact pad from the first surface comprises chemical mechanical planarization.

7 . The method of claim 1 , wherein the first metal contact pad has an uneven top surface to provide greater volume for thermal expansion relative to the second metal contact pad.

8 . The method of claim 1 , further comprising:
providing a second substrate having a second bonding surface including a plurality of conductive interconnects; direct hybrid bonding the first bonding surface of the first substrate to the second bonding surface of the second substrate without intervening adhesive, including directly bonding the first metal contact pad and the second metal contact pad to corresponding conductive interconnects of the second substrate.

9 . The method of claim 8 , wherein direct hybrid bonding comprises heating the first and second substrates to expand the first metal contact pad and the second metal contact pad into electrical and physical contact with the corresponding conductive interconnects of the second substrate.

10 . A microelectronic assembly, comprising:
a first substrate comprising a first through substrate via (TSV) and a first bonding surface configured for direct hybrid bonding; a first metal contact pad at the first bonding surface, the first metal contact pad aligned with and in electrical contact with the first TSV; and a second metal contact pad at the first bonding surface, the second metal contact pad not aligned with any TSV in the first substrate, wherein the first metal contact pad is thinner in a dimension normal to the first bonding surface compared to the second metal contact pad, wherein the first metal contact pad is recessed by a first recess depth from an upper insulating surface of the first bonding surface; the second metal contact pad is recessed by a second recess depth from the upper insulating surface of the first bonding surface; and the first recess depth is greater than the second recess depth.

11 . The microelectronic assembly of claim 10 , wherein the first metal contact pad is positioned directly over the first TSV.

12 . The microelectronic assembly of claim 10 , wherein the first metal contact pad has a larger surface area than the second metal contact pad.

13 . The microelectronic assembly of claim 10 , where the first substrate includes a second bonding surface on a side opposite the first bonding surface.

Assignees

• Adeia Semiconductor Bonding Technologies Inc

Inventors

• Gao Guilian
• Lee Bongsub
• Fountain Jr Gaius Gillman
• Uzoh Cyprian Emeka
• Mirkarimi Laura Wills
• Haba Belgacem
• Katkar Rajesh

Classifications

• H10W90/792

  between multiple chips · CPC title

• H10W80/327

  characterised by the direct bonding of insulating parts, e.g. of silicon oxide layers · CPC title

• H10W72/952

  comprising metals or metalloids, e.g. PbSn, Ag or Cu · CPC title

• H10W72/923

  Bond pads having multiple stacked layers · CPC title

• H10W72/0198

  batch processes · CPC title