Binary, ternary and bit serial compute-in-memory circuits

Patent metadata

Field	Value
Publication number	US-10860682-B2
Application number	US-202016839013-A
Country	US
Kind code	B2
Filing date	Apr 2, 2020
Priority date	Sep 28, 2018
Publication date	Dec 8, 2020
Grant date	Dec 8, 2020

Abstract

A binary CIM circuit enables all memory cells in a memory array to be effectively accessible simultaneously for computation using fixed pulse widths on the wordlines and equal capacitance on the bitlines. The fixed pulse widths and equal capacitance ensure that a minimum voltage drop in the bitline represents one least significant bit (LSB) so that the bitline voltage swing remains safely within the maximum allowable range. The binary CIM circuit maximizes the effective memory bandwidth of a memory array for a given maximum voltage range of bitline voltage.

First claim

What is claimed is:

1. An integrated circuit comprising:
a memory array of memory cells to store a binary weight matrix;
a memory access circuit of bitlines having equal capacitance and wordlines driven with pulses of fixed duration based on an input vector, the pulses to activate one or more memory cells in the memory array; and
the memory access circuit to enable an activated bitcell in the memory array to cause a voltage drop in a bitline to which the activated bitcell is coupled, the voltage drop equivalent to voltage drops caused by other activated memory cells in the memory array.

2. An integrated circuit as in claim 1 , the memory access circuit including a wordline driver to modulate the pulses of fixed duration based on the input vector, wherein the pulses activate the one or more memory cells in the memory array based on binary weights of the binary weight matrix, the binary weights stored in the memory cells.

3. An integrated circuit as in claim 2 , further comprising a capacitor circuit coupled to the bitlines to accumulate bitline voltages after voltage drops into a voltage output, the voltage output to represent a binary dot product of the input vector and the binary weight matrix stored in the memory array, the capacitor circuit including:
a column switch capacitor coupled to a bitline to accumulate a bitline voltage after voltage drops caused by activated memory cells coupled to the bitline, an accumulated bitline voltage not exceeding an allowable voltage swing; and
wherein the accumulated bitline voltage represents a positive integer value of an output vector equal to the dot product of the input vector and the binary weight matrix.

4. An integrated circuit as in claim 2 , further comprising a capacitor circuit coupled to the bitlines to accumulate bitline voltages after voltage drops into a voltage output, the voltage output to represent a binary dot product of the input vector and the binary weight matrix stored in the memory array, wherein:
binary weights of the binary weight matrix include multibit binary weights stored as binary integers in a row of consecutive memory cells spanning multiple columns of the memory array; and
the capacitor circuit includes a weighted column switch capacitor for each column of memory cells, the weighted column switch capacitor capable of charge sharing with neighboring capacitors spanning the multiple columns of the memory array, the capacitor circuit to:
disconnect a binary weighted fraction of each weighted column switch capacitor during charge sharing with neighboring capacitors, wherein the binary weighted fraction of each weighted column switch capacitor represents a ratio of weighted column switch capacitors across neighboring capacitors, the ratio based on a power of two.

5. An integrated circuit as in claim 2 , further comprising a capacitor circuit coupled to the bitlines to accumulate bitline voltages after voltage drops into a voltage output, the voltage output to represent a binary dot product of the input vector and the binary weight matrix stored in the memory array, wherein:
bitlines of the memory access circuit include differential bitlines to double an allowable voltage swing caused by activated memory cells;
binary weights of the binary weight matrix include signed binary weights, wherein the activated bitcell in which a signed binary weight is stored is enabled to cause voltage drops to the differential bitlines; and
the capacitor circuit coupled to the differential bitlines includes a differential column switch capacitor for each column of the memory array, the differential column switch capacitor to:
accumulate differential bitline voltages after voltage drops, an accumulated differential bitline voltage not exceeding a doubled allowable voltage swing;
determine a differential voltage output between the accumulated differential bitline voltage; and
wherein the differential voltage output for each column of the memory array represents a signed integer value of an output vector equal to the dot product of the input vector and the binary weight matrix.

6. An integrated circuit as in claim 5 , wherein the input vector represents a ternary input value and:
a first pulse of fixed duration based on the input vector represents a ternary value of one, the first pulse to enable activated memory cells to cause voltage drops in a first one of the differential bitlines;
a second pulse of fixed duration based on the input vector represents a ternary value of negative one, the second pulse to enable activated memory cells to cause voltage drops to a second one of the differential bitlines; and
no pulse based on the input vector representing a zero ternary value to enable no memory cells to cause voltage drops to any of the differential bitlines.

7. An integrated circuit as in claim 5 , wherein:
binary weights of the binary weight matrix include multibit binary weights stored as signed binary integers, wherein the activated memory cells in which the signed binary integers are stored are enabled to cause voltage drops in the differential bitlines; and
the capacitor circuit includes a negation circuit coupled to a column of the memory array corresponding to a bitcell in which a most significant bit of a multibit binary weight is stored, the negation circuit to invert an accumulated differential bitline voltage caused by the activated memory cells.

8. An integrated circuit as in claim 5 , wherein:
binary weights of the binary weight matrix include multibit binary weights stored as signed binary integers, wherein the activated memory cells in which the signed binary integers are stored are enabled to cause voltage drops in the differential bitlines; and
the capacitor circuit includes a weighted differential column switch capacitor coupled to a column of the memory array, the weighted differential column switch capacitor capable of charge sharing with neighboring capacitors spanning multiple columns of the memory array, the capacitor circuit further to:
disconnect a binary weighted fraction of each weighted differential column switch capacitor during charge sharing of neighboring capacitors, wherein the binary weighted fraction of each weighted differential column switch capacitor represents a ratio of weighted differential column switch capacitors across neighboring capacitors, the ratio based on a power of two; and
wherein the capacitor circuit further includes a negation circuit to swap the differential voltage output for each column of the memory array.

9. An integrated circuit as in claim 1 , wherein the memory cells of the memory array are any of a 6T SRAM and an 8T SRAM memory cell.

10. An apparatus, comprising:
a compute-in-memory (CIM) circuit, the CIM circuit comprising a computation circuit coupled to a memory array of memory cells for storing a binary weight matrix, the computation circuit comprising:
precharged bitlines of equal capacitance coupled to columns of memory cells of the memory array, and
wordlines coupled to rows of memory cells of the memory array; and
wherein the computation circuit to:
generate pulses of fixed duration across the rows of memory cells based on an input vector to the computation circuit, and
capture on the precharged bitlines an amount of voltage drop for memory cells that discharge to the precharged bitlines in response to the pulses of fixed duration, the amount of voltage drop for a bitcell equivalent to an amount of voltage drop for any other bitcell that discharges to the precharged bitlines.

11. The apparatus of claim 10 , wherein further comprising:
column switch capacitors coupled to the precharged bitlines of equal capacitance;
the computation circuit to a

Assignees

• Intel Corp

Inventors

• Knag Phil
• Chen Gregory K
• Kumar Raghavan
• Sumbul Huseyin Ekin
• Sharma Abhishek
• Manipatruni Sasikanth
• Mathuriya Amrita
• Krishnamurthy Ram
• Young Ian A

Classifications

• G11C11/419 Primary

  Read-write [R-W] circuits · CPC title

• G11C7/12

  Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines · CPC title

• G11C11/418

  Address circuits · CPC title

• G06F9/3001

  Arithmetic instructions · CPC title

• G11C7/1006

  Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor · CPC title