Semiconductor device and method of manufacturing the semiconductor device

Patent metadata

Field	Value
Publication number	US-12477737-B2
Application number	US-202418657059-A
Country	US
Kind code	B2
Filing date	May 7, 2024
Priority date	Sep 29, 2020
Publication date	Nov 18, 2025
Grant date	Nov 18, 2025

Abstract

A semiconductor device and a method of manufacturing the semiconductor device. The semiconductor device including a stacked body including conductive patterns and insulating patterns that are alternately stacked, a filling layer configured to pass through the stacked body, a first channel layer configured to pass through the stacked body and coupled to the filling layer, a second channel layer configured to pass through the stacked body and coupled to the filling layer, a first interposed layer configured to pass through the stacked body and disposed between the first channel layer and the filling layer, a second interposed layer configured to pass through the stacked body and disposed between the second channel layer and the filling layer, and a memory layer surrounding the filling layer, the first and second channel layers, and the first and second interposed layers.

First claim

What is claimed is:

1 . A method of manufacturing a semiconductor device, comprising:
forming a stacked body; forming a first hole configured to pass through the stacked body; sequentially forming a memory layer, a preliminary channel layer, and a preliminary interposed layer in the first hole; separating the preliminary interposed layer into a plurality of interposed layers by etching the preliminary interposed layer; separating the preliminary channel layer into a plurality of channel layers; and forming a filling layer coupled to the interposed layers and the channel layers, an entirety of an inside wall of each of the plurality of channel layers is in contact with each of the plurality of interposed layers.

2 . The method according to claim 1 , wherein:
a second hole is defined by the preliminary interposed layer, and separating the preliminary interposed layer into the plurality of interposed layers comprises forming a third hole by expanding the second hole.

3 . The method according to claim 2 , wherein separating the preliminary channel layer into the plurality of channel layers comprises etching the preliminary channel layer through the third hole.

4 . The method according to claim 2 , wherein a sidewall of the preliminary channel layer is exposed by the third hole.

5 . The method according to claim 1 , wherein forming the filling layer comprises:
forming a protrusion that fills a space between the memory layer and a corresponding interposed layer.

6 . The method according to claim 1 , wherein forming the filling layer comprises:
forming a filling part that fills a space between a first portion and a second portion of a corresponding interposed layer.

7 . The method according to claim 1 , wherein:
the interposed layers comprise first interposed layers comprising first interposed layers spaced apart from each other and second interposed layers disposed between the first interposed layers, and separating the preliminary channel layer into the plurality of channel layers comprises: removing portions of first adjacent parts of the preliminary channel layer adjacent to the first interposed layers and removing second adjacent parts of the preliminary channel layer adjacent to the second interposed layers.

8 . The method according to claim 2 , wherein:
separating the preliminary channel layer into the plurality of channel layers comprises forming a first cavity between respective interposed layers and the memory layer, and the first cavity is coupled to the third hole.

Assignees

• Sk Hynix Inc

Inventors

• Lee Dong Hun
• Park Mi Seong
• Jang Jung Shik
• Choi Jung Dal
• Park In Su

Classifications

• H10B63/845

  the switching components being connected to a common vertical conductor · CPC title

• H10B63/34

  of the vertical channel field-effect transistor type · CPC title

• H10B41/27

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title

• H10B43/35

  with cell select transistors, e.g. NAND · CPC title

• H10B43/10

  characterised by the top-view layout · CPC title