Etch back and film profile shaping of selective dielectric deposition

US12476144B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-12476144-B2
Application numberUS-202117544337-A
CountryUS
Kind codeB2
Filing dateDec 7, 2021
Priority dateDec 7, 2021
Publication dateNov 18, 2025
Grant dateNov 18, 2025

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  1. Title

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  2. Abstract

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  5. First independent claim

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Abstract

Official abstract text for this publication.

Self-aligned semiconductor device structures and techniques for fabrication thereof are provided. In one aspect, a self-aligned semiconductor device structure includes: at least one first conductive element embedded in a first dielectric; a second dielectric disposed selectively on the first dielectric relative to the at least one first conductive element; and at least one second conductive element present in the second dielectric that is fully aligned with the at least one first conductive element. A liner can be disposed on the second dielectric and which separates the second dielectric from the at least one second conductive element. A method of forming a self-aligned semiconductor device structure is also provided.

First claim

Opening claim text (preview).

What is claimed is: 1 . A structure, comprising: at least one first conductive element embedded in a first dielectric; a second dielectric disposed selectively on the first dielectric relative to the at least one first conductive element; at least one second conductive element present in the second dielectric that is fully aligned with the at least one first conductive element; and a liner disposed on the second dielectric, wherein the liner is present along a top surface of the second dielectric and along only an upper portion of sidewalls of the at least one second conductive element such that the liner separates the upper portion of the at least one second conductive element from the second dielectric. 2 . The structure of claim 1 , wherein, at a juncture of the at least one first conductive element and the at least one second conductive element, sidewalls of the at least one first conductive element are aligned with sidewalls of the at least one second conductive element. 3 . The structure of claim 1 , wherein the liner comprises a material selected from the group consisting of: aluminum oxide (Al 2 O 3 ), zinc oxide (ZnO), titanium oxide (TiO 2 ), and combinations thereof. 4 . The structure of claim 1 , wherein the sidewalls of the at least one second conductive element are tapered such that a top of the at least one second conductive element has a width W 1 and a bottom of the at least one second conductive element has a width W 2 , and wherein W 1 >W 2 . 5 . The structure of claim 1 , wherein the sidewalls of the at least one second conductive element are bowed such that a top of the at least one second conductive element has a width W 1 , a bottom of the at least one second conductive element has a width W 2 , and a middle of the at least one second conductive element has a width W 3 , wherein W 3 >W 1 , and wherein W 3 >W 2 . 6 . The structure of claim 1 , wherein the first dielectric and the second dielectric each comprises a material selected from the group consisting of: silicon oxide (SiOx), organosilicate glass (SiCOH), carbon-rich SiCN, SiCNO, porous organosilicate glass (pSiCOH), pSiCN, pSiCNO and combinations thereof. 7 . The structure of claim 1 , wherein the at least one first conductive element and the at least one second conductive element comprise a metal selected from the group consisting of: copper (Cu), tungsten (W), cobalt (Co), ruthenium (Ru), copper manganese (CuMn), copper aluminum (CuAl), and combinations thereof. 8 . The structure of claim 1 , wherein the at least one first conductive element directly contacts the at least one second conductive element.

Assignees

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Classifications

  • by using sacrificial placeholders, e.g. using sacrificial plugs · CPC title

  • in via holes or trenches · CPC title

  • by selectively depositing, e.g. by using selective CVD or plating · CPC title

  • Vias, e.g. via plugs · CPC title

  • the thin functional dielectric layers being temporary, e.g. sacrificial layers · CPC title

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What does patent US12476144B2 cover?
Self-aligned semiconductor device structures and techniques for fabrication thereof are provided. In one aspect, a self-aligned semiconductor device structure includes: at least one first conductive element embedded in a first dielectric; a second dielectric disposed selectively on the first dielectric relative to the at least one first conductive element; and at least one second conductive ele…
Who is the assignee on this patent?
IBM
What technology area does this patent fall under?
Primary CPC classification H10W20/069. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Nov 18 2025 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 12 related publications on this page (citations in our corpus or others sharing the same primary CPC).