Selective deposition of dielectrics on ultra-low k dielectrics

Patent metadata

Field	Value
Publication number	US-10692755-B2
Application number	US-201816169121-A
Country	US
Kind code	B2
Filing date	Oct 24, 2018
Priority date	Oct 24, 2018
Publication date	Jun 23, 2020
Grant date	Jun 23, 2020

Abstract

A method for fabricating a semiconductor device includes forming a via in a first dielectric layer arranged on a metal layer. The via exposes a portion of the metal layer. The method includes forming a trench in the first dielectric layer. The method further includes depositing, by a selective process, a second dielectric layer on the first dielectric layer such that the second dielectric layer lines sidewalls of the via and the trench and is selectively deposited onto the first dielectric layer.

First claim

What is claimed is:

1. A method of fabricating a semiconductor device, the method comprising:
forming a via in a first dielectric layer arranged on a metal layer, the via exposing a portion of the metal layer;
forming a trench in the first dielectric layer;
forming a self-assembled monolayer on the portion of the metal layer exposed by an opening in the via; and
depositing, by a selective process, a second dielectric layer on the first dielectric layer such that the second dielectric layer lines sidewalls of the via and the trench and is selectively deposited onto the first dielectric layer.

2. The method of claim 1 , wherein the dielectric layer has a k value of about 1.8 to about 4.0.

3. The method of claim 1 further comprising removing the self-assembled monolayer from the portion of the metal layer exposed by the opening.

4. The method of claim 1 , wherein the trench stops within the first dielectric layer.

5. The method of claim 1 , wherein depositing the second dielectric layer comprises depositing a precursor with a higher inherent reactivity on the first dielectric layer compared to the metal layer.

6. The method of claim 1 , wherein the second dielectric layer comprises SiO 2 , SiN, SiOC, hydrogenated silicon carbon oxide (SiCOH), SiCH, SiCNH, high density plasma oxide, borophosphosilicate glass (BPSG), TiO 2 , TiSiO, ZrO, ZnO, or Al 2 O 3 .

7. A method of fabricating a semiconductor device, the method comprising:
forming an opening through a metal layer and a first dielectric layer;
forming a self-assembled monolayer on exposed surfaces of the metal layer; and
depositing, by a selective process, a second dielectric layer on the first dielectric layer such that the second dielectric layer lines sidewalls of the opening and is selectively deposited onto the first dielectric layer.

8. The method of claim 7 , wherein the first dielectric layer has a k value of about 1.8 to about 4.0.

9. The method of claim 7 further comprising, subsequent to depositing the second dielectric layer, removing the self-assembled monolayer from the metal layer.

10. The method of claim 7 further comprising, subsequent to depositing the second dielectric layer, forming a second opening in the metal layer.

11. The method of claim 7 , wherein depositing the second dielectric layer comprises depositing a precursor with a higher inherent reactivity on the first dielectric layer compared to the metal layer.

12. A semiconductor device comprising:
an opening within a first dielectric layer that extends to and exposes a portion of a metal layer;
a self-assembled monolayer on portion of the metal layer that is exposed by the opening; and
a second dielectric layer selectively contacting the first dielectric layer and lining sidewalls of the trench.

13. The semiconductor device of claim 12 , wherein the first dielectric layer has a k value of about 1.8 to about 4.0.

14. The semiconductor device of claim 12 further comprising a metal filling the opening.

15. The semiconductor device of claim 12 further comprising a second opening in the first dielectric layer.

16. The semiconductor device of claim 15 , wherein the second opening stops in the first dielectric layer.

17. The semiconductor device of claim 16 , wherein the second dielectric layer is also deposited onto sidewalls of the second opening.

Assignees

• IBM

Inventors

• Shobha Hosadurga
• Wojtecki Rudy J
• Arellano Noel
• De Silva Ekmini A

Classifications

• H10P76/2043

  using an anti-reflective coating · CPC title

• H10P76/405

  characterised by their composition, e.g. multilayer masks · CPC title

• H10P50/287

  by chemical means · CPC title

• H10P50/283

  by chemical means · CPC title

• H10W20/0765

  the thin functional dielectric layers being temporary, e.g. sacrificial layers · CPC title