Display device

Patent metadata

Field	Value
Publication number	US-12475832-B2
Application number	US-202418420460-A
Country	US
Kind code	B2
Filing date	Jan 23, 2024
Priority date	Jan 31, 2023
Publication date	Nov 18, 2025
Grant date	Nov 18, 2025

Abstract

The present disclosure relates to a display device. A display device according to an exemplary embodiment of the present disclosure includes a display panel in which a plurality of pixels is disposed, a timing controller which generates and outputs drive signals required to drive the display panel, a first communication line which is electrically connected between the timing controller and a first memory and is electrically connected to an external device, a second communication line which is connected between the timing controller and a second memory and is electrically connected to the external device and a line controller which controls whether to use the second communication line depending on whether the first communication line is used.

First claim

The invention claimed is:

1 . A display device, comprising:
a display panel in which a plurality of pixels is disposed; a timing controller configured to generate and output control signals for driving the display panel; a first communication line which is electrically connected between the timing controller and a first memory and is electrically connected to an external device; a second communication line which is electrically connected between the timing controller and a second memory and is electrically connected to the external device; a line controller configured to control whether to use the second communication line based on whether the first communication line is used; and a switch electrically connected to the second communication line, wherein the line controller turned off the switch when determining that the first communication line is in use and the switch disconnected the second communication line, wherein the line controller determines whether the first communication line is used based on a serial clock signal and a serial data signal transmitted between the timing controller and the first memory to output a control signal which controls whether to use the second communication line, wherein the line controller includes: a usage section determination circuit which determines a start section which starts use of the first communication line to output a start signal and determines an end section which ends the use of the first communication line to output an end signal, based on the serial clock signal and the serial data signal; an initialization circuit which outputs an initialization signal to initialize the usage section determination circuit when the start signal and the end signal are input; and an output circuit which outputs the control signal which controls whether to use the second communication line according to the start signal and the end signal, wherein the output circuit outputs the control signal to disconnect the second communication line when the start signal of high level and the end signal of low level is input and outputs the control signal to electrically connect the second communication line when the start signal of high level and the end signal of high level is input.

2 . The display device according to claim 1 , wherein the first communication line is an inter-integrated circuit communication line and the second communication line is a serial peripheral interface communication line.

3 . The display device according to claim 1 , wherein:
when it is determined that the first communication line is in use, the line controller outputs the control signal which controls the second communication line not to be used, and when it is determined that the first communication line is not in use, the line controller outputs the control signal which controls the second communication line to be used.

4 . The display device according to claim 1 , wherein the usage section determination circuit includes:
a first flip flop configured to output the start signal based on the serial clock signal and the serial data signal; and a second flip flop configured to output the end signal based on the serial clock signal and the serial data signal.

5 . The display device according to claim 4 , wherein when the serial clock signal is input to an input pin and a clear pin of the first flip flop, the serial clock signal input to the first flip flop is a high level signal, and the serial data signal is a falling edge, the usage section determination circuit outputs the start signal and when the serial clock signal which is input to the second flip flop is a high level signal and the serial data signal is a rising edge, outputs the end signal.

6 . The display device according to claim 5 , wherein the usage section determination circuit further includes an inverter gate electrically connected to the first flip flop.

7 . The display device according to claim 4 , wherein when the serial clock signal input to the first flip flop is the high level signal, and the serial data signal is the falling edge, the usage section determination circuit outputs the start signal.

8 . The display device according to claim 1 , wherein the initialization circuit includes an AND gate which outputs the initialization signal when the start signal and the end signal are input.

9 . The display device according to claim 8 , wherein the initialization circuit further includes a buffer gate which is electrically connected to the AND gate to output the initialization signal to the usage section determination circuit.

10 . The display device according to claim 1 , wherein the output circuit is an XOR gate.

11 . The display device according to claim 1 ,
wherein the switch is turned on/off according to the control signal output from the output circuit.

12 . A display device, comprising:
a display panel; a timing controller configured to generate a control signal for driving the display panel; a first communication line via which the timing controller is electrically connected with an external device; a switch; a second communication line via which and the switch the timing controller is also electrically connected with the external device; and a line controller configured to, when determining that the first communication line is in use, output a control signal to the switch such that the switch is turned off, wherein the line controller is configured to turn off the switch when determining that the first communication line is in use and disconnect the switch from the second communication line, wherein the line controller determines whether the first communication line is used based on a serial clock signal and a serial data signal transmitted between the timing controller and the external device to output a control signal which controls whether to use the second communication line, wherein the line controller includes: a usage section determination circuit which determines a start section which starts use of the first communication line to output a start signal and determines an end section which ends the use of the first communication line to output an end signal, based on the serial clock signal and the serial data signal; an initialization circuit which outputs an initialization signal to initialize the usage section determination circuit when the start signal and the end signal are input; and an output circuit which outputs the control signal which controls whether to use the second communication line according to the start signal and the end signal, wherein the output circuit outputs the control signal to disconnect the second communication line when the start signal of high level and the end signal of low level is input and outputs the control signal to electrically connect the second communication line when the start signal of high level and the end signal of high level is input.

Assignees

• Lg Display Co Ltd

Inventors

• Shin Beomjun
• Ryu Gyeongho

Classifications

• G09G2300/0814

  used for selection purposes, e.g. logical AND for partial update · CPC title

• G09G2300/0819

  used for counteracting undesired variations, e.g. feedback or autozeroing · CPC title

• G09G2300/0857

  Static memory circuit, e.g. flip-flop · CPC title

• G09G2370/00

  Aspects of data communication · CPC title

• G09G3/3208 Primary

  organic, e.g. using organic light-emitting diodes [OLED] · CPC title