Display device

Patent metadata

Field	Value
Publication number	US-10007631-B2
Application number	US-201615093489-A
Country	US
Kind code	B2
Filing date	Apr 7, 2016
Priority date	Apr 28, 2015
Publication date	Jun 26, 2018
Grant date	Jun 26, 2018

Abstract

There is provided a display device including an input unit configured to connect an external device to a serial peripheral interface (SPI) through a plurality of connection lines, a switching unit configured to connect the input unit and a flash memory of a driving board to the SPI, a data register configured to output connection setting data for determining a connection state of the switching unit, and a timing controller configured to output a control signal for determining the connection setting data according to an input of a write enable line among the plurality of connection lines.

First claim

What is claimed is:

1. A display device comprising:
an input unit configured to connect an external device to a serial peripheral interface (SPI) through a plurality of connection lines;
a switching unit configured to connect the input unit and a flash memory of a driving board to the SPI;
a data register configured to output connection setting data for determining a connection state of the switching unit; and
a timing controller configured to output a control signal for determining the connection setting data according to an input of a write enable (write EN) line among the plurality of connection lines,
wherein the flash memory is configured to store unevenness correction data of each of a plurality of pixels of the display device.

2. The display device of claim 1 , further comprising a converter configured to generate connection setting data through an inter-integrated circuit (I2C) interface by receiving the control signal from the timing controller.

3. The display device of claim 1 , wherein the switching unit comprises:
a first switch circuit configured to selectively connect the timing controller and the flash memory to each other; and
a second switch circuit configured to selectively connect the flash memory and the input unit to each other.

4. The display device of claim 3 , wherein, when the input of the write EN line is at a logic high, the first switch circuit is activated, and the second switch circuit is deactivated.

5. The display device of claim 3 , wherein, when the input of the write EN line is at a logic low, the second switch circuit is activated, and the first switch circuit is deactivated.

6. The display device of claim 3 , wherein, when the input of the write EN line is at a logic high, the connection setting data comprises data for connecting the first switch circuit.

7. The display device of claim 3 , wherein, when the input of the write EN line is at a logic low, the connection setting data comprises data for connecting the second switch circuit.

8. A method for connecting a control circuit and source circuit of a display device to each other, the method comprising:
connecting, by an input unit, an external device to a serial peripheral interface (SPI) through a plurality of connection lines;
connecting, by a switching unit, the input unit and a flash memory of a driving board to the SPI;
outputting, by a data register, connection setting data for determining a connection state of the switching unit; and
outputting, by a timing controller, a control signal for determining the connection setting data according to an input of a write enable (write EN) line among the plurality of connection lines,
wherein the flash memory is configured to store unevenness correction data of each of a plurality of pixels of the display device.

9. A system for connecting a control circuit and source circuit of a display device to each other, the system comprising means for:
connecting an external device to a serial peripheral interface (SPI) through a plurality of connection lines;
connecting an input unit and a flash memory of a driving board to the SPI through a switching unit;
outputting connection setting data for determining a connection state of the switching unit; and
outputting a control signal for determining the connection setting data according to an input of a write enable (write EN) line among the plurality of connection lines,
wherein the flash memory is configured to store unevenness correction data of each of a plurality of pixels of the display device.

Assignees

• Samsung Display Co Ltd

Inventors

• Park Min Young
• Pyun Ki Hyun

Classifications

• G06F2212/7206

  Reconfiguration of flash memory system · CPC title

• G06F13/4282

  on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247) · CPC title

• G06F12/0246

  in block erasable memory, e.g. flash memory · CPC title

• G06F13/4022 Primary

  using switching circuits, e.g. switching matrix, connection or expansion network (G06F13/4009 takes precedence) · CPC title