Protocol auto-detection

Patent metadata

Field	Value
Publication number	US-12132810-B2
Application number	US-201816224092-A
Country	US
Kind code	B2
Filing date	Dec 18, 2018
Priority date	Dec 18, 2018
Publication date	Oct 29, 2024
Grant date	Oct 29, 2024

Abstract

A device includes an interface. The interface includes a plurality of pins. The interface further includes first components configured to interpret signals received at the plurality of pins according to a first protocol. The device further includes second components configured to the interpret signals received at the plurality of pins according to a second protocol. The first components are configured to disable the second components in response to a determination that the signals received at the pins correspond to the first protocol. Further, the second components are configured to disable the first components in response to a determination that the signals received at the pins correspond to the second protocol.

First claim

What is claimed is:

1. A method comprising:
receiving signals at terminals of an interface having first components configured to detect an inter-integrated circuit (I2C) protocol, and second components, separate from the first components, configured to detect a serial peripheral interface (SPI) protocol;
concurrently detecting and interpreting the signals at each of the first components and the second components, wherein the first components are configured to detect and interpret only signals corresponding to the 12 C protocol and the second components are configured to detect and interpret only signals corresponding to the SPI protocol;
determining, by the second components, whether the signals received at the interface correspond to the SPI protocol by counting pulses on a serial clock signal and comparing the pulses to a complete frame;
transmitting a first reset signal from the first components to the second components to disable the second components in response to the second components determining that the signals received at the terminals correspond to the I2C protocol; and
transmitting a second reset signal from the second components to the first components to disable the first components in response to the first components determining that the signals received at the terminals correspond to the SPI protocol.

2. The method of claim 1 , including interpreting future signals received at the interface using the first components while the second components are disabled.

3. The method of claim 1 , wherein the first components transmit the first reset signal to the second components in response to decoding a device identifier in the signals received at the terminals.

4. The method of claim 1 , wherein one of the signals received at the terminals of the interface is interpreted as a serial clock line (SCL) signal by the first components, and as an inverted chip select signal (CSN) by the second components.

5. The method of claim 1 , wherein the second components transmit the second reset signal to the first components in response to decoding a device identifier in the signals received at the terminals.

6. A semiconductor device comprising:
an interface including:
a plurality of terminals;
first components configured to detect and interpret only signals received at the terminals according to an inter-integrated circuit (I2C) protocol by counting pulses on a first serial clock signal and comparing the pulses to a complete frame; and
second components configured to, concurrently with the first components, detect and interpret only signals received at the terminals according to a serial peripheral interface (SPI) protocol by counting pulses on a second serial clock signal and comparing the pulses to a complete frame, wherein the first components are configured to send a first reset signal to the second components in response to a determination that the signals correspond to the I2C protocol, and wherein the second components are configured to send a second reset signal to the first components in response to a determination that the signals correspond to the SPI protocol; and
an electrically erasable programmable read-only memory (EEPROM) configured to store data received via the interface.

7. The semiconductor device of claim 6 , wherein the semiconductor device corresponds to an analog monitoring and control device configured to operate based on the data stored in the EEPROM.

8. The semiconductor device of claim 6 , wherein the first components are configured to interpret a first terminal as a first clock input for the I2C protocol, and wherein the second components are configured to interpret a second terminal as a second clock input for the SPI protocol.

9. The semiconductor device of claim 6 , including look-up tables configured to store information received via the interface.

10. A device comprising:
an interface including:
terminals configured to receive signals;
first components configured to detect and interpret the only signals according to inter-integrated circuit (I2C) protocol by counting pulses on a first serial clock signal and comparing the pulses to a complete frame; and
second components, separate from the first components, configured to concurrently detect and interpret only signals according to serial peripheral interface (SPI) protocol by counting pulses on a second serial clock signal and comparing the pulses to a complete frame, wherein the first components are configured to send a first reset signal to the second components in response to a determination that the signals correspond to the I2C protocol, and wherein the second components are configured to send a second reset signal to the first components in response to a determination that the signals correspond to the SPI protocol.

11. The device of claim 10 , wherein the first components include a first shift register and a first finite state machine, and wherein the second components include a second shift register and a second finite state machine.

12. The device of claim 10 , wherein the first components are configured to interpret a first terminal of the terminals as a first clock input for the I2C protocol, and wherein the second components are configured to interpret a second terminal as a second clock input for the SPI protocol.

13. The device of claim 12 , wherein the first components are configured to interpret the second terminal as a data input for the I2C protocol.

14. The device of claim 10 , wherein the first components are configured to interpret:
a first terminal as an I2C serial clock line (SCL) input;
a second terminal as an I2C serial data (SDA) input;
a third terminal as an I2C 0th bit address (A0) input;
a fourth terminal as an I2C first bit address (A1) input; and
a fifth terminal as an I2C second bit address (A2) input, and wherein the second components are configured to interpret:
the first terminal as an SPI inverted chip select (CSN) input;
the second terminal as an SPI ground input;
the third terminal as an SPI serial data out (SDO) terminal;
the fourth terminal as an SPI serial data in (SDI) input; and
the fifth terminal as an SPI serial clock (SCLK) input.

15. The device of claim 10 , wherein the first components are configured to interpret:
a first terminal as an I2C serial clock line (SCL) input;
a second terminal as an I2C 0th bit address (A0) input;
a third terminal as an I2C first bit address (A1) input;
a fourth terminal as an I2C second bit address (A2) input; and
a fifth terminal as an I2C serial data (SDA) input, and wherein the second components are configured to interpret:
the first terminal as an SPI inverted chip select (CSN) input;
the second terminal as an SPI serial data in (SDI) input;
the third terminal as an SPI serial data out (SDO) input;
the fourth terminal as an SPI interrupt request (IRQ) input; and
the fifth terminal as an SPI serial clock (SCLK) input.

16. The device of claim 10 , wherein the first components are configured to interpret:
a first terminal as an I2C serial clock line (SCL) input;
a second terminal as an I2C 0th bit address (A0) input;
a third terminal as an I2C first bit address (A1) input; and
a fourth terminal as an I2C serial data (SDA) input, and wherein the second components are configured to interpret:
the first terminal as an SPI inverted chip select (CSN) input;
the second terminal as an SPI serial data in (SDI) input;
the third terminal as an SPI serial data out (SDO) input; and
the fourth terminal as an SPI serial clock (SCLK) input.

17. The device of claim 10 , wherei

Assignees

• Texas Instruments Inc

Inventors

• Brouse Keith Charles
• Snedeker Michael Douglas
• Cheung Hugo

Classifications

• H04L69/14

  Multichannel or multilink protocols · CPC title

• G06F13/4282 Primary

  on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247) · CPC title

• H04L69/18 Primary

  Multiprotocol handlers, e.g. single devices capable of handling multiple protocols · CPC title