Array substrate and display panel

Patent metadata

Field	Value
Publication number	US-12471373-B2
Application number	US-202117919547-A
Country	US
Kind code	B2
Filing date	Nov 17, 2021
Priority date	Mar 19, 2021
Publication date	Nov 11, 2025
Grant date	Nov 11, 2025

Abstract

An array substrate and a display panel, relating to the technical field of display. The array substrate includes a base substrate, and a thin film transistor group which is provided on one side of the base substrate and includes at least two thin film transistors, the thin film transistors being stacked in a direction perpendicular to the base substrate.

First claim

What is claimed is:

1 . An array substrate, comprising:
a base substrate; and a thin film transistor group arranged on a side of the base substrate, wherein the thin film transistor group comprises at least two thin film transistors, and the thin film transistors are stacked in a direction perpendicular to the base substrate, wherein the thin film transistor group comprises a first thin film transistor and a second thin film transistor, the first thin film transistor comprises a first active layer and a first source and drain layer, and the second thin film transistor comprises a second active layer and a second source and drain layer; and wherein the first source and drain layer comprises a first pole and a second pole, the first active layer comprises a first subsection and a second subsection, the first subsection and the second subsection have a first included angle, the first subsection is connected to the first pole, and the second subsection is connected to the second pole.

2 . The array substrate according to claim 1 , wherein
the first thin film transistor is arranged on a side of the base substrate, and the second thin film transistor is arranged on a side of the first thin film transistor away from the base substrate.

3 . The array substrate according to claim 2 , wherein the first thin film transistor further comprises:
a first gate layer arranged on a side of the base substrate, wherein the first gate layer comprises a first gate; and a first gate insulating layer arranged on a side of the first gate layer away from the base substrate, wherein the first gate insulating layer covers a surface of the first gate layer; wherein the first active layer is arranged on a side of the first gate insulating layer away from the base substrate, the first pole covers one end of the first active layer, and the second pole covers the other end of the first active layer.

4 . The array substrate according to claim 3 , wherein the second thin film transistor further comprises:
a second gate layer arranged on a side of the first thin film transistor away from the base substrate, wherein the second gate layer comprises a second gate; and a second gate insulating layer arranged on a side of the second gate layer away from the base substrate, wherein the second gate insulating layer covers a surface of the second gate layer; wherein the second active layer is arranged on a side of the second gate insulating layer away from the base substrate, and the second source and drain layer comprises a third pole covering one end of the second active layer and a fourth pole covering the other end of the second active layer, and wherein orthographic projections of the third pole and the first pole on the base substrate at least partially overlap, orthographic projections of the fourth pole and the second pole on the base substrate at least partially overlap, and the orthographic projection of the second pole on the base substrate is located at least partially outside an orthographic projection of the second thin film transistor on the base substrate.

5 . The array substrate according to claim 2 , wherein the first thin film transistor further comprises:
a shielding layer arranged on a side of the base substrate, wherein the first active layer is arranged on a side of the shielding layer away from the base substrate; a first gate insulating layer arranged on a side of the first active layer away from the base substrate; a first gate layer arranged on a side of the first gate insulating layer away from the base substrate, wherein the first gate layer comprises a first gate; and a first interlayer insulating layer arranged on a side of the first gate layer away from the base substrate, wherein the first interlayer insulating layer covers a surface of the first gate layer away from the base substrate, and the first interlayer insulating layer covers side surfaces of the first gate layer and the first gate insulating layer; wherein the first source and drain layer comprises a first pole and a second pole, wherein the first pole covers a part of a surface of the first interlayer insulating layer away from the base substrate, passes through the first interlayer insulating layer, and is connected to one end of the first active layer; and wherein the second pole covers a part of the surface of the first interlayer insulating layer away from the base substrate, passes through the first interlayer insulating layer, and is connected to the other end of the first active layer.

6 . The array substrate according to claim 5 , wherein the second active layer is arranged on a side of the first thin film transistor away from the base substrate, and the second thin film transistor further comprises:
a second gate insulating layer arranged on a side of the second active layer away from the base substrate; a second gate layer arranged on a side of the second gate insulating layer away from the base substrate, wherein the second gate layer comprises a second gate; and a second interlayer insulating layer arranged on a side of the second gate layer away from the base substrate, wherein the second interlayer insulating layer covers a surface of the second gate layer away from the base substrate, and the second interlayer insulating layer covers side surfaces of the second gate layer and the second gate insulating layer; wherein the second source and drain layer comprises a third pole and a fourth pole, wherein the third pole covers a part of a surface of the second interlayer insulating layer away from the base substrate, passes through the second interlayer insulating layer, and is connected to one end of the second active layer; and the fourth pole covers a part of the surface of the second interlayer insulating layer away from the base substrate, passes through the second interlayer insulating layer, and is connected to the other end of the second active layer; and wherein projections of the third pole and the first pole on the base substrate at least partially overlap, and an orthographic projection of the second pole on the base substrate is located at least partially outside an orthographic projection of the second thin film transistor on the base substrate.

7 . The array substrate according to claim 4 , wherein the thin film transistor group further comprises:
a first passivation layer arranged between the first thin film transistor and the second thin film transistor, and arranged on a side of the first source and drain layer away from the base substrate; and a first planarization layer arranged on a side of the first passivation layer away from the base substrate.

8 . The array substrate according to claim 4 , wherein the thin film transistor group further comprises:
a second passivation layer arranged on a side of the second source and drain layer away from the base substrate; and a second planarization layer arranged on a side of the second passivation layer away from the base substrate.

9 . The array substrate according to claim 4 , wherein the array substrate further comprises:
a first scan line arranged in the same layer as the first gate layer, and connected to the first gate; a second scan line arranged in the same layer as the second gate layer, and connected to the second gate; a first data line arranged in the same layer as the first source and drain layer, and connected to the first pole; and a second data line arranged in the same layer as the second source and drain layer, and connected to the third pole or the fourth pole.

10 . The array substrate according to claim 9 , wherein orthographic projections of the first scan line and the second scan line on the base substrate at least parti

Assignees

• Boe Technology Group Co Ltd
• Beijing Boe Technology Dev Co Ltd

Inventors

• Wang Lizhong
• Ning ce
• Zhou Tianmin
• Yang Wei
• Di Yunping
• Huang Rui
• Tong Binbin
• Lei Liping

Classifications

• H10D86/441

  Interconnections, e.g. scanning lines · CPC title

• H10D86/423

  comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO · CPC title

• H10D86/471

  having different architectures, e.g. having both top-gate and bottom-gate TFTs · CPC title

• G02F1/136209

  Light shielding layers, e.g. black matrix, incorporated in the active matrix substrate, e.g. structurally associated with the switching element · CPC title

• G02F1/13685

  Top gates · CPC title