Thin film transistor assembly, array substrate and display panel

Patent metadata

Field	Value
Publication number	US-11201179-B2
Application number	US-202016825006-A
Country	US
Kind code	B2
Filing date	Mar 20, 2020
Priority date	Sep 19, 2019
Publication date	Dec 14, 2021
Grant date	Dec 14, 2021

Abstract

Embodiments of the present disclosure provide a thin film transistor assembly, an array substrate and a display panel. The thin film transistor assembly includes a first thin film transistor and a second thin film transistor disposed on a substrate. The first thin film transistor includes a first source electrode, a first drain electrode, and a first active layer. The second thin film transistor includes a second source electrode. The first source electrode is disposed on a side of the first active layer facing towards the substrate. The first drain electrode is disposed on a side of the first active layer facing away from the substrate. An orthogonal projection of the first source electrode on the substrate overlaps an orthogonal projection of the second source electrode on the substrate.

First claim

What is claimed is:

1. A thin film transistor assembly comprising:
a first thin film transistor and a second thin film transistor disposed on a substrate, wherein:
the first thin film transistor comprises a first source electrode, a first drain electrode, and a first active layer, and the second thin film transistor comprises a second source electrode,
the first source electrode is disposed on a side of the first active layer facing towards the substrate,
the first drain electrode is disposed on a side of the first active layer facing away from the substrate,
an orthogonal projection of the first source electrode on the substrate overlaps an orthogonal projection of the second source electrode on the substrate,
the second thin film transistor further comprises a second drain electrode, and the second source electrode and the second drain electrode are disposed in a same layer as the first drain electrode, and
the first source electrode is disposed on the substrate;

a buffer layer disposed on the substrate and covering the first source electrode;
a gate insulating layer disposed on a side of the buffer layer facing away from the substrate; and
an interlayer dielectric layer disposed on a side of the gate insulating layer facing away from the substrate, the first drain electrode, the second source electrode, and the second drain electrode being disposed on a side of the interlayer dielectric layer facing away from the substrate.

2. The thin film transistor assembly of claim 1 , wherein:
the orthogonal projection of the second source electrode on the substrate covers the orthogonal projection of the first source electrode on the substrate.

3. The thin film transistor assembly of claim 1 , wherein:
the second source electrode is disposed between the first drain electrode and the second drain electrode in an arrangement direction of the first thin film transistor and the second thin film transistor.

4. The thin film transistor assembly of claim 1 , wherein:
the first thin film transistor and the second thin film transistor are both top-gate thin film transistors, or the first thin film transistor and the second thin film transistor are both bottom-gate thin film transistors.

5. The thin film transistor assembly of claim 1 , wherein:
the first active layer and a second active layer of the second thin film transistor are disposed on the buffer layer, the gate insulating layer covers the first active layer and the second active layer, a first gate electrode of the first thin film transistor and a second gate electrode of the second thin film transistor are disposed on the gate insulating layer, and the interlayer dielectric layer covers the first gate electrode and the second gate electrode.

6. The thin film transistor assembly of claim 5 , wherein:
the first source electrode is electrically connected to the first active layer through a via hole formed in the buffer layer.

7. The thin film transistor assembly of claim 1 , wherein:
a first gate electrode of the first thin film transistor and a second gate electrode of the second thin film transistor are disposed on the buffer layer, the gate insulating layer covers the first gate electrode and the second gate electrode, the first active layer and a second active layer of the second thin film transistor are disposed on the gate insulating layer, and the interlayer dielectric layer covers the first active layer and the second active layer.

8. The thin film transistor assembly of claim 7 , wherein:
the first source electrode is electrically connected to the first active layer through a via hole formed in the buffer layer and the gate insulating layer.

9. An array substrate comprising the thin film transistor assembly of claim 1 .

10. The array substrate of claim 9 , further comprising:
a light blocking layer disposed in a same layer as and spaced from the first source electrode.

11. The array substrate of claim 10 , wherein:
a material of the light blocking layer is the same as a material of the first source electrode.

12. The array substrate of claim 9 , further comprising:
a plurality of sub-pixels arranged in an array, wherein every two adjacent columns of sub-pixels constitute a pixel group, no thin film transistor is disposed between two adjacent pixel groups,
wherein in each of the pixel groups, a first gap is provided between two columns of sub-pixels, and a second gap is provided between two adjacent rows of sub-pixels, and the thin film transistor assembly is disposed in an overlap of the first gap and the second gap.

13. The array substrate of claim 12 , further comprising:
a first sub-pixel, a third sub-pixel, a second sub-pixel, and a fourth sub-pixel sequentially arranged in a 2 by 2 matrix around each thin film transistor assembly,
wherein the first thin film transistor of the thin film transistor assembly is electrically connected to the first sub-pixel, and the second thin film transistor of the thin film transistor assembly is electrically connected to the second sub-pixel.

14. A display panel comprising:
the array substrate of claim 9 .

15. The display panel of claim 14 , further comprising:
a plurality of first black matrixes disposed opposite to the array substrate, orthogonal projections of the plurality of first black matrixes on the substrate covering orthogonal projections of the first and second thin film transistors on the substrate,
wherein each of the first black matrixes has a width of 15 μm to 25 μm.

16. The display panel of claim 15 , further comprising:
a plurality of second black matrixes disposed in a same layer as the plurality of first black matrixes, an orthogonal projection of each of the plurality of second black matrixes on the substrate overlapping an orthogonal projection, on the substrate, of a gap between two adjacent pixel groups,
wherein each of the second black matrixes has a width of 5 μm to 10 μm.

17. The display panel of claim 14 , further comprising:
a plurality of first black matrixes disposed opposite to the array substrate, orthogonal projections of the plurality of first black matrixes on the substrate covering orthogonal projections of the first and second thin film transistors on the substrate; and
a plurality of second black matrixes disposed in a same layer as the plurality of first black matrixes, an orthogonal projection of each of the plurality of second black matrixes on the substrate overlapping an orthogonal projection, on the substrate, of a gap between two adjacent pixel groups, wherein each of the plurality of second black matrixes has a less width than each of the plurality of first black matrixes.

Assignees

• Ordos Yuansheng Optoelectronics Co Ltd
• Boe Technology Group Co Ltd

Inventors

• Ren Yanwei
• Tang Wulijibaier
• Li Xiaoguang
• Xu Jingyi
• Wang Yuelin
• Jia Lei
• Yu Yanan
• Zhi Guolei

Classifications

• H10D86/451

  characterised by the compositions or shapes of the interlayer dielectrics · CPC title

• H10D30/6729

  characterised by the electrodes · CPC title

• H10D86/471

  having different architectures, e.g. having both top-gate and bottom-gate TFTs · CPC title

• H10D30/6723

  having light shields · CPC title

• H10D86/441

  Interconnections, e.g. scanning lines · CPC title