Manufacturing method of array substrate, array substrate with active layer being above first electrode, and display device

Patent metadata

Field	Value
Publication number	US-10490670-B2
Application number	US-201715754120-A
Country	US
Kind code	B2
Filing date	Jun 20, 2017
Priority date	Dec 1, 2016
Publication date	Nov 26, 2019
Grant date	Nov 26, 2019

Abstract

A manufacturing method of an array substrate, an array substrate and a display device are provided. The method includes: forming a first electrode; forming a first insulation layer on the first electrode; forming a first via hole in the first insulation layer; forming an active layer on the first insulation layer, which is electrically connected with the first electrode through the first via hole; forming a gate insulation layer on the active layer; forming a first gate electrode on the gate insulation layer, which overlaps with at least part of the active layer; forming a second insulation layer on the first gate electrode and the gate insulation layer, forming a second via hole in the second insulation layer and the gate insulation layer; forming a pixel electrode on the second insulation layer, which is electrically connected with the active layer through the second via hole.

First claim

What is claimed is:

1. A manufacturing method of an array substrate, comprising:
providing a base substrate;
forming a first electrode on the base substrate;
forming a first insulation layer on a side, facing away from the base substrate, of the first electrode, and forming a first via hole in the first insulation layer;
forming an active layer on a side, facing away from the base substrate, of the first insulation layer, wherein the active layer extends into the first via hole to directly contact and be electrically connected with the first electrode;
forming a gate insulation layer on a side, facing away from the base substrate, of the active layer;
forming a first gate electrode on a side, facing away from the base substrate, of the gate insulation layer, the first gate electrode overlapping with at least part of the active layer in a direction perpendicular to the base substrate;
forming a second insulation layer on a side, facing away from the base substrate, of the first gate electrode and the gate insulation layer, and forming a second via hole in the second insulation layer and the gate insulation layer; and
forming a pixel electrode on a side, facing away from the base substrate, of the second insulation layer, the pixel electrode being electrically connected with the active layer through the second via hole.

2. The manufacturing method according to claim 1 , further comprising:
forming a common electrode on the side, facing away from the base substrate, of the second insulation layer,
wherein the common electrode and the pixel electrode are located in a same layer, and branch electrode strips of the common electrode and branch electrode strips of the pixel electrode are at least partially interdigitated with each other.

3. The manufacturing method according to claim 1 , further comprising:
forming a common electrode on the side, facing away from the base substrate, of the second insulation layer;
forming a third insulation layer on a side, facing away from the base substrate, of the common electrode, and forming a third via hole overlapping with the second via hole in the third insulation layer;
wherein the pixel electrode is formed on a side, facing away from the base substrate, of the third insulation layer, and the pixel electrode is electrically connected with the active layer through the second via hole and the third via hole.

4. The manufacturing method according to claim 1 , further comprising:
forming a fourth insulation layer on a side, facing away from the base substrate, of the pixel electrode; and
forming a common electrode on a side, facing away from the base substrate, of the fourth insulation layer.

5. The manufacturing method according to claim 1 , further comprising:
forming a light shielding layer during forming the first electrode,
wherein the light shielding layer overlaps with at least part of the active layer in the direction perpendicular to the base substrate.

6. The manufacturing method according to claim 1 , wherein the active layer is an amorphous silicon layer, a polysilicon layer or an oxide semiconductor layer.

7. The manufacturing method according to claim 6 , wherein the active layer is the polysilicon layer, and the manufacturing method of the array substrate further comprises:
doping the polysilicon layer to obtain a channel region, a first doping region located on two sides of the channel region, and a second doping region located on a side of the first doping region away from the channel region,
wherein doping concentration of the first doping region is less than doping concentration of the second doping region.

8. The manufacturing method according to claim 1 , further comprising:
forming a second gate electrode on the side, facing away from the base substrate, of the gate insulation layer,
wherein the second gate electrode overlaps with at least part of the active layer in the direction perpendicular to the base substrate.

9. An array substrate, comprising:
a base substrate;
a first electrode disposed on the base substrate;
a first insulation layer disposed on a side, facing away from the base substrate, of the first electrode, and a first via hole disposed in the first insulation layer;
an active layer disposed on a side, facing away from the base substrate, of the first insulation layer, wherein the active layer extends into the first via hole to directly contact and be electrically connected with the first electrode;
a gate insulation layer disposed on a side, facing away from the base substrate, of the active layer;
a first gate electrode disposed on a side, facing away from the base substrate, of the gate insulation layer, and the first gate electrode overlapping with at least part of the active layer in a direction perpendicular to the base substrate;
a second insulation layer disposed on a side, facing away from the base substrate, of the gate insulation layer and the first gate electrode, and a second via hole disposed in the gate insulation layer and the second insulation layer; and
a pixel electrode disposed on a side, facing away from the base substrate, of the second insulation layer, the pixel electrode being electrically connected with the active layer through the second via hole.

10. The array substrate according to claim 9 , further comprising:
a common electrode disposed on the side, facing away from the base substrate, of the second insulation layer,
wherein the common electrode and the pixel electrode are located in a same layer, and branch electrode strips of the common electrode and branch electrode strips of the pixel electrode are at least partially interdigitated with each other.

11. The array substrate according to claim 9 , further comprising:
a common electrode disposed on the side, facing away from the base substrate, of the second insulation layer;
a third insulation layer disposed on a side, facing away from the base substrate, of the common electrode,
wherein a third via hole, which overlaps with the second via hole, is disposed in the third insulation layer, and the pixel electrode is disposed on a side, facing away from the base substrate, of the third insulation layer and electrically connected with the active layer through the second via hole and the third via hole.

12. The array substrate according to claim 9 , further comprising:
a fourth insulation layer disposed on a side, facing away from the base substrate, of the pixel electrode; and
a common electrode disposed on a side, facing away from the base substrate of the fourth insulation layer.

13. The array substrate according to claim 9 , further comprising:
a light shielding layer disposed in a same layer with the first electrode,
wherein the light shield layer overlaps with at least part of the active layer in the direction perpendicular to the base substrate.

14. The array substrate according to claim 9 , wherein the active layer is an amorphous silicon layer, a polysilicon layer or an oxide semiconductor layer.

15. The array substrate according to claim 9 , further comprising:
a second gate electrode disposed on the side, facing away from the base substrate, of the gate insulation layer,
wherein the second gate electrode overlaps with at least part of the active layer in the direction perpendicular to the base substrate.

16. A display device, comprising the array substrate according to claim 9 .

17. The array substrate according to claim 1 , wherein
the first electrode is a source electrode or a drain electrode, and a part of the pixel electrode contacting the active layer is

Assignees

• Boe Technology Group Co Ltd
• Ordos Yuansheng Optoelectronics Co Ltd

Inventors

• Li Feng
• Shi Dawei
• Wang Fengguo
• Liu Hong
• Wu Xinguo
• Wang Zifeng
• Ma Bo
• Guo Zhixuan
• Li Yuanbo

Classifications

• H10P30/204

  into Group IV semiconductors · CPC title

• H10P30/22

  using masks · CPC title

• H10P30/21

  of electrically active species · CPC title

• H10P14/3802

  Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth · CPC title

• H10P14/3454

  Amorphous · CPC title