Process and temperature compensated word line underdrive scheme for SRAM

Patent metadata

Field	Value
Publication number	US-12469549-B2
Application number	US-202318231461-A
Country	US
Kind code	B2
Filing date	Aug 8, 2023
Priority date	Aug 29, 2022
Publication date	Nov 11, 2025
Grant date	Nov 11, 2025

Abstract

Disclosed herein is an electronic device, including a plurality of row decoders. Each row decoder includes decoder logic generating an initial word line signal and word line driver circuitry generating an inverse word line signal at an intermediate node from the initial word line signal, and generating a word line signal at a word line node from the inverse word line signal. A word line underdrive p-channel transistor has a source coupled to the intermediate node, a drain coupled to a word line underdrive sink, and a gate controlled based upon the inverse word line signal. Negative bias generation circuitry generates the negative bias voltage at a gate of the word line underdrive p-channel transistor when the initial word line signal is at a logic high, and couples the gate of the word line underdrive p-channel transistor to ground when the initial word line signal is at a logic low.

First claim

The invention claimed is:

1 . An electronic device, comprising:
a plurality of row decoders, each row decoder comprising:
decoder logic configured to generate an initial word line signal;
word line driver circuitry configured to generate an inverse word line signal at an intermediate node from the initial word line signal, and to generate a word line signal at a word line node from the inverse word line signal;
a word line underdrive transistor having a first conduction node coupled to the intermediate node, a second conduction node coupled to a word line underdrive sink, and a gate controlled based upon the inverse word line signal; and
negative bias generation circuitry configured to generate a negative bias voltage at the gate of the word line underdrive transistor when the initial word line signal is at a logic high, and to couple the gate of the word line underdrive transistor to ground when the initial word line signal is at a logic low.

2 . The electronic device of claim 1 , wherein the word line underdrive transistor is a p-channel transistor having a source coupled to the intermediate node and a drain coupled to the word line underdrive sink.

3 . The electronic device of claim 1 , wherein the negative bias generation circuitry comprises:
a drive inverter having an input coupled to the inverse word line signal, an output coupled to the gate of the word line underdrive transistor, a first power terminal connected to a voltage supply node, and a second power terminal connected to a node; a negative bias generating n-channel transistor having a drain connected to the node, a source connected to ground, and a gate connected to receive a negative bump signal, the negative bump signal being generated based upon a clock signal; and a capacitor connected between the node and a delayed version of the negative bump signal.

4 . The electronic device of claim 3 , wherein the drive inverter comprises: a p-channel transistor having a source connected to the voltage supply node, a drain connected to the drain of the word line underdrive transistor, and a gate connected to a net node; and an n-channel transistor having a drain connected to the drain of the word line underdrive transistor, a source connected to the node of the negative bias generation circuitry, and a gate connected to the net node; and wherein the negative bias generation circuitry further comprises an inverter receiving the inverse word line signal as input and providing output to the net node.

5 . The electronic device of claim 3 , wherein the input of the drive inverter is coupled to the inverse word line signal through an inverter.

6 . The electronic device of claim 1 , further comprising a pre-charge circuit configured to pre-charge the word line underdrive sink to a predetermined intermediate voltage prior to assertion of the negative bias voltage.

7 . The electronic device of claim 6 , wherein the pre-charge circuit pre-charges the word line underdrive sink to approximately one-half of a supply voltage level.

8 . The electronic device of claim 1 , wherein a temperature and process compensated source control signal generator, comprising the negative bias generation circuitry, is disposed in a global control block common to all of the plurality of row decoders.

9 . The electronic device of claim 1 , wherein the word line driver circuitry comprises a first CMOS inverter stage that generates the inverse word line signal at the intermediate node and a second CMOS inverter stage that generates the word line signal at the word line node.

10 . The electronic device of claim 1 , wherein the initial word line signal is clocked by an address clock derived from a global clock, and the negative bias generation circuitry generates the negative bias voltage in synchronization with a delayed version of the global clock.

11 . The electronic device of claim 3 , wherein the negative bump signal is generated by a NAND gate receiving as inputs an inverse global clock signal and a delayed version thereof.

12 . The electronic device of claim 3 , further comprising an inverter chain configured to produce the delayed version of the negative bump signal.

13 . The electronic device of claim 1 , wherein the word line underdrive transistor is sized smaller than an equivalent transistor without negative bias generation, by virtue of the negative bias voltage reducing its effective threshold voltage.

14 . The electronic device of claim 1 , further comprising a dummy memory array having a plurality of dummy cells that generate a driver output signal to track process, voltage, and temperature variations.

Assignees

• St Microelectronics Int Nv

Inventors

• Kumar Ashish
• Arya Dipti

Classifications

• G11C8/08

  Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines · CPC title

• G11C7/227

  Timing of memory operations based on dummy memory elements or replica circuits · CPC title

• G11C8/18

  Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals · CPC title

• G11C7/04

  with means for avoiding disturbances due to temperature effects · CPC title

• G11C11/418 Primary

  Address circuits · CPC title