Apparatus for improving read stability

Patent metadata

Field	Value
Publication number	US-9922702-B1
Application number	US-201715397035-A
Country	US
Kind code	B1
Filing date	Jan 3, 2017
Priority date	Jan 3, 2017
Publication date	Mar 20, 2018
Grant date	Mar 20, 2018

Abstract

Described is an apparatus which comprises: a pass-gate; a sleep transistor configured as a diode-connected device controllable by the pass-gate; and a word-line driver coupled to the sleep transistor and the pass-gate.

First claim

We claim:

1. An apparatus comprising:
a first transistor coupled to a first supply node;
a word-line driver coupled in series with the first transistor, wherein the word-line driver has a second supply node coupled to the first transistor, and wherein the word-line driver is to provide a word-line signal for a memory; and
a second transistor coupled to the second supply node and to a gate terminal of the first transistor, wherein the second transistor is controllable by a gated low power mode signal, wherein the second transistor has a source/drain terminal coupled to a gate of the first transistor, and wherein the second transistor has a drain/source terminal coupled to the second power supply node.

2. The apparatus of claim 1 , wherein the word-line driver comprises:
a third transistor coupled to the first and second transistors; and
a fourth transistor coupled in series with the third transistor, wherein gate terminals of the third and fourth transistor are controllable by an input word-line signal.

3. The apparatus of claim 1 comprises a tristate-able driver having an output coupled to the first and second transistors.

4. The apparatus of claim 3 , wherein the tristate-able driver comprises a fifth transistor coupled to the first supply node and to the first and second transistors, and wherein the fifth transistor is controllable by a low power mode signal.

5. The apparatus of claim 4 , wherein the tristate-able driver comprises a sixth transistor coupled in series with the fifth transistor, and controllable by the low power mode signal.

6. The apparatus of claim 5 , wherein the tristate-able driver comprises a seventh transistor coupled in series with the sixth transistor, and wherein the seventh transistor is to be driven by a logic gate which is to provide the gated low power mode signal.

7. The apparatus of claim 6 , wherein second transistor is to be driven by the logic gate.

8. The apparatus of claim 6 , wherein the logic gate comprises one of: NAND gate, NOR, AND, or OR gate.

9. The apparatus of claim 1 , wherein the supply node is a power supply node.

10. An apparatus comprising:
a pass-gate;
a sleep transistor configured as a diode-connected device controllable by the pass-gate, wherein the pass-gate has a source/drain terminal coupled to a gate of the sleep transistor, and wherein the pass-gate has a drain/source terminal coupled to a power supply node; and
a word-line driver coupled to the sleep transistor and the pass-gate via the power supply node.

11. The apparatus of claim 10 comprises tristate-able driver coupled to the sleep transistor.

12. The apparatus of claim 11 , wherein the tristate-able driver includes a footer transistor, and wherein a gate terminal of the footer transistor is coupled to the pass-gate.

13. The apparatus of claim 12 comprises a logic gate having an output coupled to the gate terminal of the footer transistor.

14. A system comprising:
a processor;
a memory comprising a static random access memory (SRAM);
a word-line driver coupled to the memory, wherein the word-line driver comprises:
a first transistor coupled to a first supply node;
a driver coupled in series with the first transistor, wherein the driver has a second supply node coupled to the first transistor, and wherein the driver is to provide a word-line signal for the memory; and
a second transistor coupled to the second supply node and to a gate terminal of the first transistor, wherein the second transistor is controllable by a gated low power mode signal, wherein the second transistor has a source/drain terminal coupled to a gate of the first transistor, and wherein the second transistor has a drain/source terminal coupled to the second power supply node; and

a wireless interface to allow the processor to communicate with another device.

15. The system of claim 14 , wherein the driver of the word-line driver comprises:
a third transistor coupled to the first and second transistors; and
a fourth transistor coupled in series with the third transistor, wherein gate terminals of the third and fourth transistor are controllable by an input word-line signal.

16. The system of claim 14 , wherein the word-line driver comprises a tristate-able driver having an output coupled to the first and second transistors.

17. The system of claim 16 , wherein the tristate-able driver comprises a fifth transistor coupled to the first supply node and to the first and second transistors, and wherein the fifth transistor is controllable by a low power mode signal.

18. The system of claim 17 , wherein the tristate-able driver comprises a sixth transistor coupled in series with the fifth transistor, and controllable by the low power mode signal.

19. The system of claim 18 , wherein the tristate-able driver comprises a seventh transistor coupled in series with the sixth transistor, and wherein the seventh transistor is to be driven by a logic gate.

20. The system of claim 19 , wherein the second transistor is driven by the logic gate.

Assignees

• Intel Corp

Inventors

• Shanmugam Amarnath
• Basu Anik
• Ferrera Steve P
• Rajamani Srinivas
• Merchant Feroze A

Classifications

• H03K19/20

  characterised by logic function, e.g. AND, OR, NOR, NOT circuits (H03K19/003 - H03K19/01 take precedence) · CPC title

• G11C11/419 Primary

  Read-write [R-W] circuits · CPC title

• G11C11/412

  using field-effect transistors only · CPC title

• G11C8/08

  Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines · CPC title