SRAM write driver with improved drive strength

Patent metadata

Field	Value
Publication number	US-10249361-B2
Application number	US-201414154678-A
Country	US
Kind code	B2
Filing date	Jan 14, 2014
Priority date	Jan 14, 2014
Publication date	Apr 2, 2019
Grant date	Apr 2, 2019

Abstract

A subsystem configured to write data to a static random access memory cell employs a single N-channel MOS device connected to ground in each leg of the bi-stable memory cell to overdrive the stored data. The subsystem implements the dual control required to effect matrix operation of the SRAM cell in the gate circuit of the single N-channel MOS device in the drive path. Specifically, the column select signal controls a semiconductor junction that interrupts the data connection to the gate. In this manner, the column select control is removed from the drive path, thus increasing drive strength. Further, a second semiconductor junction connects the gate of the single NMOS device in the drive path when the gate signal is interrupted.

First claim

The invention claimed is:

1. A subsystem, comprising:
a first bit line driver that drives a single bit line of a memory cell, writes a data bit to the memory cell, and includes:
a first field effect transistor (FET) that includes:
a first FET gate terminal that receives a first write select line as an input,
a first FET first data terminal that transmits a first data line that transports the data bit, and
a first FET second data terminal directly coupled to the first data line;

a second FET that includes:
a second FET pate terminal that receives the first write select line as an input, and
a second FET data terminal that is directly coupled to the first FET first data terminal; and

a first circuit element that includes:
a first input terminal directly coupled to the first FET first data terminal and the second FET data terminal, and
a first circuit data terminal that is directly coupled to the single bit line of the memory cell.

2. The subsystem of claim 1 , wherein the first FET comprises a P-channel field effect transistor, and the second FET and the first circuit element comprise N-channel field effect transistors.

3. The subsystem of claim 1 , further comprising:
a second bit line driver that writes the inverse of the data bit to the memory cell and including:
a third FET that includes: is
a third FET gate terminal that receives the first write select line as an input, and
a third FET data terminal that transmits a second data line that transports the inverse of the data bit,

a fourth FET that includes:
a fourth FET gate terminal that receives the first write select line as an input, and
a fourth FET data terminal that is coupled to the third FET data terminal; and

a second circuit element coupled to the memory cell, wherein the second circuit element includes a second input terminal directly coupled to the third FET terminal and the fourth FET terminal.

4. The subsystem of claim 3 , wherein the third FET comprises a P-channel field effect transistor, and the fourth FET and the second circuit element comprise N-channel field effect transistors.

5. The subsystem of claim 3 , wherein the first bit line driver further includes a third circuit element that is directly coupled to the first circuit element and includes a third input terminal that receives the second data line as an input.

6. The subsystem of claim 5 , wherein, in response to the second write data line being activated, the seventh-third circuit element pulls the first input terminal to ground.

7. The subsystem of claim 6 , wherein the third element comprises an N-channel field effect transistor.

8. The subsystem of claim 3 , wherein the second bit line driver further includes a fourth circuit element that is directly coupled to the second circuit element and includes a fourth input terminal that receives the first data line as an input.

9. The subsystem of claim 8 , wherein, in response to the first write data line being activated, the fourth circuit element pulls the second input terminal to ground.

10. The subsystem of claim 9 , wherein the fourth circuit element comprises an N-channel field effect transistor.

11. A computer-implemented method for performing write operations with memory cells, the method comprising:
driving, by a first bit line driver, a single bit line of a memory cell by:
causing a first write select line to activate a first field effect transistor (FET) included in the first bit line driver, wherein the first FET includes a first FET gate terminal that receives the first write select line, a first FET first data terminal that outputs a data bit that is transported by a first data line, and a first FET second data terminal directly coupled to the first data line; and
causing the first write select line to activate a second FET included in the first bit line driver, wherein the second FET includes a second FET gate terminal that receives the first write select line, and a second FET data terminal circuit element that is directly coupled to the first FET first data terminal;
wherein a first circuit element included in the first bit line driver includes a first input terminal directly coupled to the first FET first data terminal and the second FET data terminal and a first circuit data terminal that is directly coupled to the single bit line of the memory cell; and
writing, by the first bit line driver, the data bit to the memory cell.

12. The computer-implemented method of claim 11 , further comprising:
causing the first write select line to activate a third FET included in a second bit line driver, wherein the third FET includes a third FET gate terminal that receives the first write select line, and a third FET data terminal that outputs the inverse of the data bit that is transported by a second data line; and
causing the first write select line to activate a a fourth FET included in a second bit line driver, wherein the fourth FET includes a fourth FET gate terminal that receives the first write select line, and a fourth FET data terminal that is coupled to the third FET data terminal:
wherein a second circuit element included in the second bit line driver includes a second input terminal directly coupled to the third FET data terminal and the fourth FET data terminal.

13. The computer-implemented method of claim 12 , further comprising causing a third circuit element to pull the first input terminal to ground in response to activation of the second data line.

14. The computer-implemented method of claim 12 , further comprising causing a fourth circuit element to pull second input terminal to ground in response to activation of the first data line.

15. A system, comprising:
a memory cell; and
a first bit line driver that drives a single bit line of the memory cell, writes a data bit to the memory cell, and includes:
a first field effect transistor (FET) that includes:
a first FET gate terminal that receives a first write select line as an input,
a first FET first data terminal that transmits a first data line that transports the data bit, and
a first FET second data terminal directly coupled to the first data line;

a second FET that includes:
a second FET gate terminal that receives the first write select line as an input, and
a second FET data terminal that is directly coupled to the first FET first data terminal: and

a first circuit element that is coupled to the memory cell, wherein the first circuit element includes:
a first input terminal directly coupled to the first FET first data terminal and the second FET data terminal, and
a first circuit data terminal that is directly coupled to the single bit line of the memory cell.

16. The system of claim 15 , further comprising:
a second bit line driver coupled to the memory cell and including:
a third FET that includes:
a third FET gate terminal that receives the first write select line as an input, and
a third FET data terminal that transmits a second data line that transports the inverse of the data bit,

a fourth FET that includes:
a fourth FET gate terminal that receives the first write select line as an input, and
a fourth FET data terminal that is coupled to the third FET data terminal: and

a second circuit element coupled to the memory cell, wherein the second circuit element includes a second input terminal directly coupled to the third FET terminal and the fourth FET terminal.

17. The system of claim 16 , wherein the first bit line driver further includes a third circuit element that is directly coupled to the third-first circuit element and includes a

Assignees

• Nvidia Corp

Inventors

• Wang Eugene
• Chen Gavin
• Shen Demi

Classifications

• G11C11/419 Primary

  Read-write [R-W] circuits · CPC title