Display substrate and manufacturing method thereof, display device

Patent metadata

Field	Value
Publication number	US-12469444-B2
Application number	US-202418799091-A
Country	US
Kind code	B2
Filing date	Aug 9, 2024
Priority date	Apr 10, 2020
Publication date	Nov 11, 2025
Grant date	Nov 11, 2025

Abstract

A display substrate and manufacturing method thereof, and a display device are provided. The display substrate includes a base substrate, and a shift register unit and a first clock signal line that are on the base substrate, the first clock signal line extends along a first direction on the base substrate and is configured to provide a first clock signal to the shift register unit, the shift register unit includes an input circuit, an output circuit, a first control circuit and an output control circuit, and the first control circuit includes a first control switch and a second control switch, an active layer of the first control switch and an active layer of the second control switch are a continuous control semiconductor layer, the control semiconductor layer extends along the first direction.

First claim

What is claimed is:

1 . A display substrate, comprising: a base substrate, and a shift register unit, a first power line, a second power line, a plurality of clock signal line which comprise a first clock signal line and a trigger signal line, that are on the base substrate,
wherein the first clock signal line and the trigger signal line extend along a first direction on the base substrate and is configured to provide a first clock signal to the shift register unit; the shift register unit comprises an input circuit, an output circuit, a first control circuit and an output control circuit; the input circuit is configured to input an input signal to a first node in response to the first clock signal; the output circuit is configured to output an output signal to an output terminal; the first control circuit is configured to control a level of a second node in response to a level of the first node and the first clock signal; the output control circuit is configured to control a level of the output terminal under control of the level of the second node, wherein the first control circuit comprises a first control switch and a second control switch, an active layer of the first control switch and an active layer of the second control switch are a continuous control semiconductor layer, the control semiconductor layer extends along the first direction, and a gate electrode of the first control switch and a gate electrode of the second control switch extend along a second direction different from the first direction and are arranged side by side in the first direction.

2 . The display substrate according to claim 1 , wherein an included angle between the first direction and the second direction ranges from 70 degrees and 90 degrees;
wherein the plurality of clock signal line further comprises a second clock signal line, extends along the first direction on the base substrate and is configured to provide a second clock signal to the shift register unit, and the display substrate further comprises a first power line and a second power line that are configured to respectively supply a first voltage and a second voltage to the shift register unit; wherein a width of the first clock signal line and a width of the second clock signal line are greater than a width of the second power line.

3 . The display substrate according to claim 1 , wherein the shift register unit further comprises a voltage stabilization circuit,
the voltage stabilization circuit is connected to the first node and a third node, and is configured to stabilize a level of the third node; the output circuit is connected to the third node, and is configured to output the output signal to the output terminal under control of the level of the third node; wherein the display substrate further comprises a first power line and a second power line that are configured to respectively supply a first voltage and a second voltage to the shift register unit, wherein the voltage stabilization circuit comprises a voltage stabilization switch, the second power line comprises a protrusion portion protruding in the second direction; a second electrode of the second control switch and a gate electrode of the voltage stabilization switch are both connected to the protrusion portion of the second power line to receive the second voltage; and a first electrode of the voltage stabilization switch is connected to the third node, and a second electrode of the voltage stabilization switch is connected to the first node; wherein a width of the first power line is greater than a width of the second power line.

4 . The display substrate according to claim 1 , wherein the input circuit comprises an input switch, and an active layer of the input switch is in a strip shape extending along the second direction;
the input switch comprises a first gate electrode, a second gate electrode and a connection electrode connecting the first gate electrode and the second gate electrode; and the connection electrode comprises a first part which is connected to the first gate electrode and extends along the first direction, a second part connected to the second gate electrode, and a third part which extends along the second direction and is connected to the first part and the second part, and the third part of the connection electrode is connected to the first clock signal line to receive the first clock signal.

5 . The display substrate according to claim 4 , wherein an active layer of the first control switch, an active layer of the second control switch and an active layer of the input switch are arranged side by side in the second direction.

6 . The display substrate according to claim 4 , wherein a first electrode of the input switch is connected to a signal input electrode through a first connection wire extending along the second direction to receive the input signal.

7 . The display substrate according to claim 4 , wherein the shift register unit further comprises a wire transfer electrode,
wherein the first electrode of the input switch is electrically connected to a first end of the wire transfer electrode, the wire transfer electrode is in a different layer from the active layer of the input switch, and a second end of the wire transfer electrode is connected to a first end of the first connection wire, the wire transfer electrode is in a different layer from the first connection wire, a second end of the first connection wire is electrically connected to the signal input electrode, and the wire transfer electrode is in a same layer as the signal input electrode.

8 . The display substrate according to claim 7 , wherein the shift register unit further comprises a first insulation layer, a second insulation layer, and a third insulation layer,
wherein the first insulation layer is between the active layer of the input switch and the first connection wire, and the second insulation layer and third insulation layer are between the first connection wire and the wire transfer electrode; and the first electrode of the input switch is in a same layer as the wire transfer electrode, and the second end of the wire transfer electrode is connected to the first end of the first connection wire through a via hole penetrating the second insulation layer and the third insulation layer, and the second end of the first connection wire is electrically connected to the signal input electrode through a via hole penetrating the second insulation layer and the third insulation layer.

9 . The display substrate according to claim 4 , wherein the display substrate further comprises a second clock signal line configured to provide a second clock signal to the shift register unit, and the shift register unit further comprises a second control circuit; and
the second control circuit is connected to the first node and the second node, and is configured to control the level of the first node under control of the level of the second node and the second clock signal.

10 . The display substrate according to claim 9 , wherein the second control circuit comprises a first noise reduction switch and a second noise reduction switch;
an active layer of the first noise reduction switch and an active layer of the second noise reduction switch are a continuous noise reduction semiconductor layer, and the noise reduction semiconductor layer extends along the first direction and is arranged side by side with the active layer of the input switch in the first direction; a gate electrode of the first noise reduction switch and a gate electrode of the second noise reduction switch extend along the second direction and are arranged side by side in the first direction; and the first electrode of the

Assignees

• Chengdu Boe Optoelect Tech Co
• Boe Technology Group Co Ltd

Inventors

• Yu Pengfei
• Bai Lu
• Dai Jie
• Han Linhong

Classifications

• H10K59/131

  Interconnections, e.g. wiring lines or terminals · CPC title

• G11C19/28

  using semiconductor elements (G11C19/14, G11C19/36 take precedence) · CPC title

• G09G2330/08

  Fault-tolerant or redundant circuits, or circuits in which repair of defects is prepared · CPC title

• G09G2330/02

  Details of power systems and of start or stop of display operation · CPC title

• G09G2310/08

  Details of timing specific for flat panels, other than clock recovery · CPC title