Stage circuit and scan driver including the same

Patent metadata

Field	Value
Publication number	US-11127340-B2
Application number	US-202017009880-A
Country	US
Kind code	B2
Filing date	Sep 2, 2020
Priority date	Jan 16, 2020
Publication date	Sep 21, 2021
Grant date	Sep 21, 2021

Abstract

A stage circuit includes a first substage circuit unit connected to first through third input terminals receiving a start signal, a first clock signal, and a second clock signal, respectively. The first substage circuit unit generates first and second operation signals based on the start signal and the first and second clock signals, and supplies a first scan signal to a first output terminal based on the first and second operation signals. The stage circuit further includes a second substage circuit unit connected to the third input terminal and a fourth input terminal receiving a third clock signal. The second substage circuit unit supplies a second scan signal to a second output terminal based on the first and second operation signals, the second clock signal, and the third clock signal. The first and second scan signals include a pulse of a low voltage level and a high voltage level, respectively.

First claim

What is claimed is:

1. A stage circuit, comprising:
a first substage circuit unit connected to a first input terminal which receives a start signal, a second input terminal which receives a first clock signal, and a third input terminal which receives a second clock signal,
wherein the first substage circuit unit generates a first operation signal and a second operation signal based on the start signal, the first clock signal, and the second clock signal, and supplies a first scan signal to a first output terminal based on the first operation signal and the second operation signal; and
a second substage circuit unit connected to the third input terminal and a fourth input terminal which receives a third clock signal,
wherein the second substage circuit unit supplies a second scan signal to a second output terminal based on the first operation signal, the second operation signal, the second clock signal, and the third clock signal,
wherein the first scan signal includes a pulse of a low voltage level, and the second scan signal includes a pulse of a high voltage level.

2. The stage circuit according to claim 1 , wherein each of the first substage circuit unit and the second substage circuit unit is connected to a first power input terminal and a second power input terminal,
the first power input terminal receives a first power set to a gate-off voltage, and
the second power input terminal receives a second power set to a gate-on voltage.

3. The stage circuit according to claim 2 , wherein the first substage circuit unit comprises:
a first output unit connected to the third input terminal and the first power input terminal,
wherein the first output unit supplies the first scan signal to the first output terminal in response to a voltage of a first node and a voltage of a second node;
a first driver connected to the first input terminal and the first power input terminal,
wherein the first driver controls a voltage of a third node in response to the first clock signal and the second clock signal; and
a second driver connected to the second input terminal, the first power input terminal, the second power input terminal, and the third node,
wherein the second driver controls the voltage of the first node and the voltage of the second node.

4. The stage circuit according to claim 3 , wherein the first driver comprises:
a first transistor connected between the first input terminal and the third node and having a gate electrode connected to the second input terminal; and
a second transistor and a third transistor connected in series between the first power input terminal and the third node,
wherein a gate electrode of the second transistor is connected to the third input terminal, and
a gate electrode of the third transistor is connected to the first node.

5. The stage circuit according to claim 3 , wherein the first output unit comprises:
a first transistor connected between the first power input terminal and the first output terminal and having a gate electrode connected to the first node; and
a second transistor connected between the third input terminal and the first output terminal and having a gate electrode connected to the second node.

6. The stage circuit according to claim 3 , wherein the second driver comprises:
a first transistor connected between the second node and the third node and having a gate electrode connected to the second power input terminal;
a second transistor connected between the first node and the second input terminal and having a gate electrode connected to the third node;
a third transistor connected between the first node and the second power input terminal and having a gate electrode connected to the second input terminal;
a first capacitor connected between the second node and the first output terminal; and
a second capacitor connected between the first node and the first power input terminal.

7. The stage circuit according to claim 3 , wherein the first operation signal is the voltage of the first node, and the second operation signal is the voltage of the third node.

8. The stage circuit according to claim 3 , wherein the first operation signal is the voltage of the first node, and the second operation signal is the voltage of the second node.

9. The stage circuit according to claim 3 , wherein the second substage circuit unit comprises:
a second output unit connected to the fourth input terminal and the second power input terminal,
wherein the second output unit supplies the second scan signal to the second output terminal in response to a voltage of a fourth node and a voltage of a fifth node;
a third driver connected to the third input terminal, the first power input terminal, the second power input terminal, a sixth node, and a seventh node,
wherein the third driver controls the voltage of the fifth node in response to the second operation signal supplied to the sixth node and the first operation signal supplied to the seventh node; and
a fourth driver connected to the third input terminal, the second power input terminal, and the sixth node,
wherein the fourth driver controls the voltage of the fourth node, and
the sixth node is the same node as the third node, and the seventh node is the same node as the first node.

10. The stage circuit according to claim 9 , wherein the third driver comprises:
a first transistor connected between the fifth node and the seventh node and having a gate electrode connected to the second power input terminal;
a second transistor connected between the third input terminal and an eighth node and having a gate electrode connected to the fifth node;
a third transistor connected between the first power input terminal and the eighth node and having a gate electrode connected to the sixth node; and
a capacitor connected between the fifth node and the eighth node.

11. The stage circuit according to claim 9 , wherein the fourth driver comprises:
a first transistor connected between the fifth node and an eighth node and having a gate electrode connected to the second power input terminal;
a second transistor connected between the third input terminal and a ninth node and having a gate electrode connected to the eighth node;
a third transistor connected between the fourth node and the ninth node and having a gate electrode connected to the third input terminal; and
a capacitor connected between the eighth node and the ninth node.

12. The stage circuit according to claim 9 , wherein the second output unit comprises:
a first transistor connected between the fourth node and the fourth input terminal and having a gate electrode connected to the fifth node;
a second transistor connected between the fourth input terminal and the second output terminal and having a gate electrode connected to the fourth node;
a third transistor connected between the second power input terminal and the second output terminal and having a gate electrode connected to the fifth node; and
a capacitor connected between the fourth input terminal and the fourth node.

13. The stage circuit according to claim 2 , wherein the first clock signal and the second clock signal have a same period, and a high voltage supply period is set to be longer than a low voltage supply period in one period,
the second clock signal is set to a signal shifted by half a period from the first clock signal, and
the third clock signal is a signal having a phase inverted from a phase of the second clock signal.

14. The stage circuit according to claim 1 , wherein the start signal is a first scan signal of a previous first substage circuit unit or a scan start signal.

Assignees

• Samsung Display Co Ltd

Inventors

• Byun Min Woo
• Park Jong Won
• Hyun Chae Han

Classifications

• G09G3/3677

  suitable for active matrices only · CPC title

• G09G3/344

  based on particles moving in a fluid or in a gas, e.g. electrophoretic devices (electrophoretic devices per se G02F1/167) · CPC title

• G09G3/3266 Primary

  Details of drivers for scan electrodes · CPC title

• G09G3/3225 Primary

  using an active matrix · CPC title

• G09G3/32

  semiconductive, e.g. using light-emitting diodes [LED] · CPC title