Power delivery architecture for high power portable devices

Patent metadata

Field	Value
Publication number	US-2022376515-A1
Application number	US-202117323833-A
Country	US
Kind code	A1
Filing date	May 18, 2021
Priority date	May 18, 2021
Publication date	Nov 24, 2022
Grant date	—

Abstract

A power architecture that uses an efficient intermediate power conversion stage between AC adaptor (and battery charger) and subsequent voltage regulators (VRs) (e.g., core VR) for processors for higher overall efficiency allowing for higher performance in a given thermal envelope and iso-system input power. Power losses from both the charger and the core VR are reduced by splitting the power as power to sustained high-power rails, and power to the rest of the platform power rails that have low residency in high-power states. The sustained high-power rails are placed under an intermediate power conversion topology which is directly powered by the adaptor. The rest of the rails along with charging of the battery are powered by the battery charger.

First claim

What is claimed is:

1 . An apparatus comprising:
a battery transistor coupled to a battery; a battery charger to control the battery transistor; a circuitry to bypass the battery charger; a first voltage regulator having an input coupled to the circuitry and the battery transistor, wherein some platform components are directly coupled to the battery transistor; and a second voltage regulator having an input coupled to an output of the first voltage regulator, wherein the second voltage regulator provides power to a processor core.

2 . The apparatus of claim 1 , wherein the first voltage regulator comprises a switch capacitor voltage regulator or a high-efficiency intermediate converter.

3 . The apparatus of claim 1 , wherein the battery charger includes a buck or buck-boost converter.

4 . The apparatus of claim 1 , wherein the battery charger receives an input supply from an external source.

5 . The apparatus of claim 1 comprises a third voltage regulator having an input coupled to the output of the first voltage regulator, wherein the third voltage regulator provides power to a graphics processor.

6 . The apparatus of claim 1 , wherein the battery charger is coupled to an adaptor.

7 . The apparatus of claim 1 , wherein the first voltage regulator is without an inductor.

8 . The apparatus of claim 1 , wherein the first voltage regulator is with an inductor.

9 . The apparatus of claim 1 , wherein the battery is a series configuration of battery cells.

10 . An apparatus comprising:
a voltage regulator to supply power to downstream power regulators that provide power to a processor core or a graphics processor; a battery charger coupled to a battery to provide power to the battery, wherein the battery charger includes a buck or buck-boost converter; and a battery transistor coupled to the battery and the voltage regulator, wherein the battery transistor is controllable by the battery charger.

11 . The apparatus of claim 10 , wherein the voltage regulator comprises a switch capacitor voltage regulator.

12 . The apparatus of claim 10 , wherein the battery charger is coupled to an adaptor.

13 . The apparatus of claim 10 , wherein the voltage regulator is with an inductor.

14 . The apparatus of claim 10 , wherein the voltage regulator without an inductor.

15 . The apparatus of claim 10 , wherein the battery is a series configuration of battery cells.

16 . A system comprising:
a processor; a graphics processor; a battery transistor coupled to a battery; a battery charger to control the battery transistor, wherein some platform components are directly coupled to the battery transistor; a circuitry to bypass the battery charger; a first voltage regulator having an input coupled to the circuitry and the battery transistor; a second voltage regulator having an input coupled to an output of the first voltage regulator, wherein the second voltage regulator provides power to the processor; a third voltage regulator having an input coupled to an output of the first voltage regulator, wherein the third voltage regulator provides power to the graphics processor; and a wireless interface to allow the processor to communicate with another device.

17 . The system of claim 16 , wherein the first voltage regulator comprises a switch capacitor voltage regulator, and wherein the first voltage regulator provides power to either of the processor or the graphics processor.

18 . The system of claim 16 , wherein the battery charger includes a buck converter.

19 . The system of claim 16 , wherein the buck converter receives an input supply from an external source.

20 . The system of claim 16 , wherein the battery charger is coupled to an adaptor, wherein the battery is a series configuration of battery cells.

Assignees

• Intel Corp

Inventors

• Singh Jagadish
• PARAKKAL Rohit
• K Tarakesava Reddy
• S Arvind
• Rajasekaran Arvindh
• Rao Raghavendra R

Classifications

• H02J7/50 Primary

  acting upon multiple batteries simultaneously or sequentially · CPC title

• H02J2105/44

  Portable electronic devices · CPC title

• H02J7/855 Primary

  with circuits adapted for supplying loads from the battery · CPC title

• H02M1/007

  Plural converter units in cascade (push-pull DC/DC converters with pre-regulator H02M3/3374; DC-AC converters following a DC-DC stage including a high frequency transformer H02M7/4807; DC-AC converters following a DC-DC conversion stage generating periodically varying voltages H02M7/4826) · CPC title

• G06F1/26

  Power supply means, e.g. regulation thereof (for memories G11C) · CPC title