Memory circuitry comprising strings of memory cells and method used in forming a memory array comprising strings of memory cells

Patent metadata

Field	Value
Publication number	US-12464713-B2
Application number	US-202217665346-A
Country	US
Kind code	B2
Filing date	Feb 4, 2022
Priority date	Feb 4, 2022
Publication date	Nov 4, 2025
Grant date	Nov 4, 2025

Abstract

Memory circuitry comprising strings of memory cells comprising memory blocks individually comprises a vertical stack comprising alternating insulative tiers and conductive tiers. Channel-material strings of memory cells extend through the insulative tiers and the conductive tiers in a memory-array region. The insulative tiers and the conductive tiers of the memory blocks extend from the memory-array region into a stair-step region. Individual of the memory blocks in the stair-step region comprise a flight of operative stairs. Individual of the operative stairs comprise one of the conductive tiers. At least some immediately-laterally-adjacent of the individual memory blocks in the stair-step region have their flights of operative stairs laterally-separated by a stack comprising two vertically-alternating different-composition insulative materials. Other embodiments, including method, are disclosed.

First claim

The invention claimed is:

1 . Memory circuitry comprising strings of memory cells, comprising:
memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers, channel-material strings of memory cells extending through the insulative tiers and the conductive tiers in a memory-array region, the insulative tiers and the conductive tiers of the memory blocks extending from the memory-array region into a stair-step region; individual of the memory blocks in the stair-step region comprising a flight of operative stairs, individual of the operative stairs comprising one of the conductive tiers; at least some immediately-laterally-adjacent of the individual memory blocks in the stair-step region having their flights of operative stairs laterally-separated by a stack comprising two vertically-alternating different-composition insulative materials; and walls that are individually laterally between the immediately-laterally-adjacent memory blocks in the memory-array region, the walls not being laterally-adjacent said flights of operative stairs, the walls individually comprising an end portion that is in the stack comprising the two vertically-alternating different-composition insulative materials.

2 . The memory circuitry of claim 1 wherein the at least some consist of every-other-one of the memory blocks.

3 . The memory circuitry of claim 1 wherein the walls individually are horizontally-longitudinally-elongated, the end portion being everywhere horizontally-longitudinally-spaced from where all of the channel-material strings extend through the insulative tiers and the conductive tiers, the end portion having a maximum lateral width that is greater than a maximum lateral width of that portion of its wall that is not horizontally-longitudinally-spaced from where all of the channel-material strings extend through the insulative tiers and the conductive tiers.

4 . The memory circuitry of claim 1 wherein the walls are comprised by a first set of walls and further comprising a second set of walls, the walls of the first and second sets being individually laterally between the immediately-adjacent memory blocks, the walls of the second set being horizontally longer than the walls of the first set.

5 . The memory circuitry of claim 4 wherein individual of the walls of the first and second sets laterally alternate every-other-one with individual of the walls of the second set.

6 . Memory circuitry comprising strings of memory cells, comprising:
memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers, channel-material strings of memory cells extending through the insulative tiers and the conductive tiers in a memory-array region, the insulative tiers and the conductive tiers of the memory blocks extending from the memory-array region into a stair-step region; individual of the memory blocks in the stair-step region comprising a flight of operative stairs, individual of the operative stairs comprising one of the conductive tiers; walls that are individually laterally between the immediately-laterally-adjacent memory blocks in the memory-array region and extending only partially into the stair-step region; and at least some immediately-laterally-adjacent of the individual memory blocks in the stair-step region having their flights of operative stairs laterally-separated by a flight of inoperative stairs.

7 . The memory circuitry of claim 6 wherein the flight of inoperative stairs comprises a stack comprising two vertically-alternating different-composition insulative materials.

8 . The memory circuitry of claim 7 wherein individual of the inoperative stairs comprise one of each of the two different-composition insulative materials.

9 . The memory circuitry of claim 8 wherein individual of the inoperative stairs comprise only one of each of the two different-composition insulative materials.

10 . The memory circuitry of claim 6 wherein the at least some consist of every-other-one of the memory blocks.

11 . The memory circuitry of claim 6 wherein the walls are comprised by a first set of walls and further comprising a second set of walls, the walls of the second set being horizontally longer than the walls of the first set.

12 . The memory circuitry of claim 11 wherein individual of the walls of the first set laterally alternate every-other-one with individual of the walls of the second set.

13 . Memory circuitry comprising strings of memory cells, the memory circuitry comprising:
memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers, channel-material strings of memory cells extending through the insulative tiers and the conductive tiers; walls that are individually laterally between immediately-laterally-adjacent of the individual memory blocks; and at least some of the walls individually comprising an end portion that is in an insulative stack comprising two vertically-alternating different-composition insulative materials, the insulative stack being within a stair step region of the memory circuitry, the walls being individually horizontally-longitudinally-elongated, the end portion being everywhere horizontally-longitudinally-spaced from where all of the channel-material strings extend through the insulative tiers and the conductive tiers, the end portion having a maximum lateral width that is greater than a maximum lateral width of that portion of its wall that is not horizontally-longitudinally-spaced from where all of the channel-material strings extend through the insulative tiers and the conductive tiers.

14 . The memory circuitry of claim 13 wherein the maximum lateral width of the end portion is less than twice as great as the maximum lateral width of that portion of its wall that is not horizontally-longitudinally-spaced from where all of the channel-material strings extend through the insulative tiers and the conductive tiers.

15 . The memory circuitry of claim 13 wherein the maximum lateral width of the end portion is at least twice as great as the maximum lateral width of that portion of its wall that is not horizontally-longitudinally-spaced from where all of the channel-material strings extend through the insulative tiers and the conductive tiers.

16 . The memory circuitry of claim 15 wherein the maximum lateral width of the end portion is at least three times as great as the maximum lateral width of that portion of its wall that is not horizontally-longitudinally-spaced from where all of the channel-material strings extend through the insulative tiers and the conductive tiers.

17 . Memory circuitry comprising strings of memory cells, comprising:
two memory-array regions having a stair-step region there-between; memory blocks in each of the two memory-array regions that individually comprise a vertical stack comprising alternating insulative tiers and conductive tiers, channel-material strings of memory cells extending through the insulative tiers and the conductive tiers in the memory blocks in the two memory-array regions; and walls that are individually laterally between immediately-adjacent of the memory blocks in the two memory-array regions, the walls comprising a first set of the walls that extend from one of the two memory-array regions into the other of the two memory-array regions across the stair-step region, the walls comprising a second set of walls that extend from one of the two memory-array regions only partially into the stair-step region.

Assignees

• Micron Technology Inc

Inventors

• Xu Lifang
• Hill Richard J
• Fukuzumi Yoshiaki
• Tessariol Paolo

Classifications

• H10P14/40

  of conductive or resistive materials · CPC title

• H10D84/01

  Manufacture or treatment · CPC title

• H10B12/0387

  Making the trench · CPC title

• H10B43/27

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title

• H10B43/10 Primary

  characterised by the top-view layout · CPC title