Integrating embedded memory with logic interconnects

Patent metadata

Field	Value
Publication number	US-12463142-B1
Application number	US-202117449797-A
Country	US
Kind code	B1
Filing date	Oct 1, 2021
Priority date	Oct 1, 2021
Publication date	Nov 4, 2025
Grant date	Nov 4, 2025

Abstract

An integration process including an etch stop layer for high density memory and logic applications and methods of fabrication are described. While various examples are described with reference to FeRAM, capacitive structures formed herein can be used for any application where a capacitor is desired. For instance, the capacitive structure can be used for fabricating ferroelectric based or paraelectric based majority gate, minority gate, and/or threshold gate.

First claim

What is claimed is:

1 . A device comprising:
a first region comprising:
a first conductive interconnect within a first level, the first conductive interconnect comprising a first lateral thickness; and
a second level above the first level, the second level comprising:
a memory device above the first conductive interconnect, the memory device comprising ferroelectric material or paraelectric material, wherein the memory device comprises a second lateral thickness and cylindrical shape;
an electrode structure coupled between the memory device and the first conductive interconnect, the electrode structure comprising a third lateral thickness, wherein the first lateral thickness and the third lateral thickness are respectively less than the second lateral thickness;
an etch stop layer comprising a dielectric material, the etch stop layer laterally surrounding the electrode structure;
a spacer on a sidewall of the memory device and on a portion of the electrode structure; and
a via electrode on the memory device; and

a second region adjacent to the first region, the second region comprising an interconnect structure, the interconnect structure comprising:
a second conductive interconnect within the first level;
a metal line within the second level; and
a via structure coupling the metal line with the second conductive interconnect, wherein at least a first portion of the via structure is adjacent to the etch stop layer, and wherein at least a second portion of the etch stop layer is on the second conductive interconnect, wherein the electrode structure has a first vertical thickness, the memory device has a second vertical thickness, the via electrode has a third vertical thickness, the via structure has a fourth vertical thickness, and the metal line has a fifth vertical thickness, wherein a sum of the first vertical thickness, the second vertical thickness and the third vertical thickness is substantially equal to a sum of the fourth vertical thickness and the fifth vertical thickness.

2 . The device of claim 1 , wherein the memory device comprises:
a first conductive layer comprising a non-Pb based perovskite metal oxide, the first conductive layer comprising a first sidewall having a first slope; a ferroelectric dielectric layer comprising a non-Pb based perovskite material on the first conductive layer, the ferroelectric dielectric layer comprising a second sidewall having a second slope; and a second conductive layer comprising non-Pb based perovskite metal oxide on the ferroelectric dielectric layer, the second conductive layer comprising a third sidewall having a third slope, wherein the first slope, the second slope and the third slope are substantially close to ninety degrees relative to a lowermost surface of the memory device.

3 . The device of claim 1 , wherein the electrode structure comprises a first cylindrical shape, and the first conductive interconnect comprises a second cylindrical shape, wherein the first lateral thickness is a first diameter and the second lateral thickness is a second diameter and the third lateral thickness is a third diameter, and wherein the third diameter is greater than the first diameter and the second diameter.

4 . The device of claim 3 , wherein a first vertical axis of the electrode structure is offset from a second vertical axis of the first conductive interconnect.

5 . The device of claim 4 , wherein a third vertical axis of the memory device is offset from the first vertical axis of the electrode structure.

6 . The device of claim 1 , wherein a sum of the first vertical thickness and the second vertical thickness is substantially equal to the fourth vertical thickness, and wherein the third vertical thickness is substantially equal to the fifth vertical thickness.

7 . The device of claim 1 , wherein a sum of the first vertical thickness and the second vertical thickness is substantially equal to the third vertical thickness, wherein the third vertical thickness is substantially equal to the fifth vertical thickness, and wherein the second vertical thickness is less than 20 nm and the third vertical thickness is greater than 30 nm but less than 200 nm.

8 . The device of claim 1 , wherein the electrode structure extends below an uppermost surface of the first conductive interconnect.

9 . The device of claim 1 , wherein the memory device is a first memory device, wherein the electrode structure is a first electrode structure, wherein the spacer is a first spacer, wherein the via electrode is a first via electrode, and wherein the device further comprises:
a third conductive interconnect laterally distant from the first conductive interconnect, wherein the third conductive interconnect is behind the first conductive interconnect; a second memory device above the second conductive interconnect; a second electrode structure coupled between the second memory device and the second conductive interconnect; a second spacer on a fourth sidewall of the second memory device; and a second via electrode on the second memory device.

10 . The device of claim 9 , wherein the device further comprises a conductive plate coupling the first via electrode and the second via electrode.

11 . The device of claim 9 , wherein the first memory device is separated from the second memory device by a spacing of less than 30 nm, and wherein the spacing is measured from a shortest distance between a fifth sidewall of the first electrode structure and a sixth sidewall of the second electrode structure.

12 . The device of claim 1 , wherein the etch stop layer has a sixth vertical thickness under the memory device and a seventh vertical thickness adjacent to the via structure, and wherein the sixth vertical thickness is greater than the seventh vertical thickness.

13 . The device of claim 12 , wherein the first vertical thickness is at least two times greater than the second vertical thickness.

14 . A device comprising:
a first region comprising:
a first conductive interconnect within a first level, the first conductive interconnect comprising a first sidewall; and
a second level above the first level, the second level comprising:
a memory device above the first conductive interconnect, the memory device comprising ferroelectric material or paraelectric material, wherein the memory device comprises a second sidewall;
an electrode structure coupled between the memory device and the first conductive interconnect, the electrode structure comprising a third sidewall, wherein the first sidewall and the second sidewall extend laterally beyond the third sidewall;
an etch stop layer comprising a dielectric material, the etch stop layer laterally surrounding the electrode structure, the etch stop layer further comprising a first portion under the memory device and a second portion adjacent the first portion, wherein the first portion comprises a first vertical thickness, and wherein the second portion comprises a second vertical thickness and a fourth sidewall;
a spacer on a fifth sidewall of the memory device and on the second portion of the etch stop layer;
a via electrode on the memory device; and
an encapsulation layer on the memory device, adjacent to the spacer and adjacent to the fourth sidewall; and

a second region adjacent to the first region, the second region comprising an interconnect structure, the interconnect structure comprising:
a second conductive interconnect within the first level;
a metal line within the second level; and
a via structure coupling the metal line with the second conductive interconnect, wherein at least a third portion of the via str

Assignees

• Kepler Computing Inc

Inventors

• Sato Noriyuki
• Guhabiswas Debraj
• Gosavi Tanay
• Mukherjee Niloy
• Mathuriya Amrita
• Manipatruni Sasikanth

Classifications

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title

• H10W90/00

  Package configurations · CPC title

• H10W70/635

  Through-vias · CPC title

• H10W70/614

  the multiple chips being integrally enclosed · CPC title

• H10W70/611

  for connecting multiple chips together · CPC title