Semiconductor package

Patent metadata

Field	Value
Publication number	US-12463126-B2
Application number	US-202218060812-A
Country	US
Kind code	B2
Filing date	Dec 1, 2022
Priority date	Jun 2, 2022
Publication date	Nov 4, 2025
Grant date	Nov 4, 2025

Abstract

A semiconductor package including a dielectric layer on a substrate and having an opening that partially exposes a top surface of the substrate, a capacitor chip on the substrate and in the opening of the dielectric layer, connection terminals between the substrate and the capacitor chip and connecting the substrate and the capacitor chip to each other, dielectric patches on the substrate and in the opening of the dielectric layer, and an under-fill filling a space between the substrate and the capacitor chip may be provided. The space between the substrate and the capacitor chip includes a first region, a second region, and a third region between the first and second regions. The connection terminals are on the first region and the second region. The dielectric patches are on the third region.

First claim

What is claimed is:

1 . A semiconductor package, comprising:
a substrate; a dielectric layer on the substrate, the dielectric layer having an opening that exposes a portion of a top surface of the substrate; a capacitor chip mounted on the substrate, the capacitor chip being within the opening of the dielectric layer in plan view; connection terminals between the substrate and the capacitor chip, the connection terminals being on a bottom surface of the capacitor chip and connected to chip pads of the capacitor chip, the connection terminals connecting the substrate and the capacitor chip to each other; dielectric patches on the substrate and in the opening of the dielectric layer; and an under-fill filling a space between the substrate and the capacitor chip, wherein the space between the substrate and the capacitor chip includes a first region, a second region, and a third region between the first region and the second region, the first and second regions being horizontally spaced apart from each other, a density of the connection terminals in the third regions is lower than a density of the connection terminals in each of the first region and the second region, wherein the connection terminals are on the first region and the second region, wherein the dielectric patches are on the third region and are completely and laterally surrounded by the under-fill, and wherein a top surface of the dielectric layer is at a same level as top surfaces of the dielectric patches.

2 . The semiconductor package of claim 1 , wherein the capacitor chip includes a silicon capacitor.

3 . The semiconductor package of claim 1 , wherein a width in a direction of the third region is greater than a diameter of each of the connection terminals, the direction being directed from the first region toward the second region.

4 . The semiconductor package of claim 1 , wherein each of the dielectric patches has a circular planar shape, a tetragonal planar shape, or a polygonal planar shape.

5 . The semiconductor package of claim 1 , wherein the dielectric patches constitute at least one column extending in a first direction that is horizontally perpendicular to a second direction from the first region toward the second region.

6 . The semiconductor package of claim 1 , wherein the dielectric patches include:
first dielectric patches; and second dielectric patches spaced apart from the first dielectric patches, wherein an interval between one of the first dielectric patches and an adjacent one of the second dielectric patches is greater than a distance between the first dielectric patches and a distance between the second dielectric patches.

7 . The semiconductor package of claim 1 , wherein, when viewed in plan, an area of each of the dielectric patches is 0.8 times to 1.2 times an area of each of the connection terminals.

8 . The semiconductor package of claim 1 , wherein the dielectric patches includes a same material as the dielectric layer.

9 . A semiconductor package, comprising:
a first substrate; a dielectric layer below the first substrate, the dielectric layer exposing a portion of the first substrate; a capacitor chip mounted on the portion of the first substrate, the portion of the first substrate being exposed by the dielectric layer, the capacitor chip being within the portion of the first substrate in plan view; an under-fill filling a space between the first substrate and the capacitor chip; connection terminals between the first substrate and the capacitor chip and electrically connecting the first substrate to the capacitor chip, the connection terminals being on a bottom surface of the capacitor chip and connected to chip pads of the capacitor chip, the connection terminals including first connection terminals in a first region and second connection terminals in a second region spaced apart from the first connection terminals by a third region; dielectric patches below the first substrate and between the first connection terminals and the second connection terminals, the dielectric patches including a same material as the dielectric layer, the dielectric patches being completely and laterally surrounded by the under-fill, each of a density of the first connection terminals in the first region and a density of the second connection terminals in the second region is greater than a density of the connection terminals in the third region; a first semiconductor chip mounted on the first substrate; and a first molding layer on the first substrate, the first molding layer covering the first semiconductor chip.

10 . The semiconductor package of claim 9 , further comprising:
a second substrate on the first molding layer; a second semiconductor chip mounted on the second substrate; a second molding layer on the second substrate and covering the second semiconductor chip; and substrate connection terminals penetrating the first molding layer on one side of the first semiconductor chip, the substrate connection terminals connecting the first substrate to the second substrate.

11 . The semiconductor package of claim 9 , wherein the capacitor chip includes a silicon capacitor.

12 . The semiconductor package of claim 9 , wherein an interval between one of the first connection terminals and an adjacent one of the second connection terminals is greater than a diameter of each of the connection terminals.

13 . The semiconductor package of claim 9 , wherein each of the dielectric patches has a circular planar shape, a tetragonal planar shape, or a polygonal planar shape.

14 . The semiconductor package of claim 9 , wherein the dielectric patches constitute at least one column in a region between the first connection terminals and the second connection terminals and extending in a first direction that is horizontally perpendicular to a second direction from the first connection terminals toward the second connection terminals.

15 . The semiconductor package of claim 9 , wherein the dielectric patches include:
first dielectric patches; and second dielectric patches spaced apart from the first dielectric patches, wherein an interval between one of the first dielectric patches and an adjacent one of the second dielectric patches is greater than a distance between the first dielectric patches and a distance between the second dielectric patches.

16 . The semiconductor package of claim 9 , wherein, when viewed in plan, an area of each of the dielectric patches is 0.8 times to 1.2 times an area of each of the connection terminals.

17 . The semiconductor package of claim 9 , wherein a bottom surface of the dielectric layer is at a same level as bottom surfaces of the dielectric patches.

18 . A semiconductor package, comprising:
a substrate; a dielectric layer exposing a mount region of the substrate; a capacitor chip mounted on the mount region of the substrate, the capacitor chip being withing the mount region of the substrate in plan view; connection terminals between the substrate and the capacitor chip and connecting the substrate and the capacitor chip, the connection terminals being on a bottom surface of the capacitor chip and connected to chip pads of the capacitor chip; dielectric patches on the mount region of the substrate; and an under-fill filling a space between the substrate and the capacitor chip, wherein the mount region includes a first region, a second region, and a third region between the first region and the second region, the first and second regions being provided with the connection terminals,

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Jungjoo
• Lee Yongkwan
• Kim Seung Hwan
• Kim Jongwan
• Park Junwoo
• Jeon Taejun
• Jo Junhyeung

Classifications

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W74/15

  on active surfaces of flip-chip devices, e.g. underfills · CPC title

• H10W90/401

  characterised by multiple insulating or insulated package substrates, interposers or RDLs · CPC title

• H10W90/00 Primary

  Package configurations · CPC title