Semiconductor package

Patent metadata

Field	Value
Publication number	US-10957629-B2
Application number	US-201916256895-A
Country	US
Kind code	B2
Filing date	Jan 24, 2019
Priority date	Jul 10, 2018
Publication date	Mar 23, 2021
Grant date	Mar 23, 2021

Abstract

A semiconductor package includes a package substrate, a flip chip coupled to the package substrate, an interposer stacked on the flip chip and including a first terminal and a second terminal at an upper surface thereof, a bonding wire which connects the first terminal and the package substrate and a mold layer which covers the interposer, the flip chip and the bonding wire. The mold layer has a signal hole which exposes the second terminal, and at least one dummy hole spaced apart from the signal hole on an upper surface of the interposer.

First claim

What is claimed is:

1. A semiconductor package comprising:
a package substrate;
a flip chip coupled to the package substrate;
an interposer stacked on the flip chip and including an interposer substrate, and a first terminal and a second terminal on an upper surface of the interposer substrate;
a bonding wire which connects the first terminal and the package substrate;
a mold layer which covers the interposer, the flip chip and the bonding wire,
wherein the mold layer has a signal hole therein which leads to and opens at the second terminal, and at least one dummy hole therein spaced apart from the signal hole and situated over the upper surface of the interposer,
wherein part of the mold layer extends over the upper surface of the interposer, and
each said at least one dummy hole extends completely through said part of the mold layer; and
a protective film on the upper surface of the interposer and exposed by each said at least one dummy hole.

2. The semiconductor package of claim 1 , wherein the first and second terminals are disposed on a first region of the upper surface of the interposer, and
the protective film is disposed on a second region of the upper surface of the interposer that is apart from the first region.

3. The semiconductor package of claim 1 , wherein respective shapes of the signal hole and each said at least one dummy hole are the same.

4. The semiconductor package of claim 1 , wherein the at least one dummy hole comprises a plurality of dummy holes each situated over the upper surface of the interposer, and
respective sizes of the signal hole and each of the dummy holes, as viewed in a plan view, are the same.

5. The semiconductor package of claim 1 , wherein respective depths of the signal hole and each said at least one dummy hole are the same.

6. The semiconductor package of claim 1 , wherein the signal hole is situated over a first region of the upper surface of the interposer,
the at least one dummy hole is situated over a second region of the upper surface of the interposer, and
the first region is located further towards an outer periphery of the upper surface of the interposer than the second region.

7. The semiconductor package of claim 1 , further comprising:
a micro bump which electrically connects the package substrate and the flip chip.

8. A semiconductor package comprising:
a lower package; and
an upper package stacked on the lower package,
wherein the lower package comprises
a package substrate,
a flip chip coupled to the package substrate,
an interposer stacked on the flip chip and including an interposer substrate, and a first terminal and a second terminal on an upper surface of the interposer substrate, and
a mold layer which covers the interposer and the flip chip,
the mold layer having a signal hole therein which leads to and is open at the second terminal, and at least one dummy hole therein spaced apart from the signal hole and situated over the upper surface of the interposer, and
wherein the at least one dummy hole is empty or filled with a non-electrically conducting medium.

9. The semiconductor package of claim 8 , wherein the lower package further includes a solder ball situated in the signal hole as disposed in contact with the second terminal,
wherein the upper package is in contact with the solder ball.

10. The semiconductor package of claim 8 , wherein the upper package includes a first memory chip and a second memory chip stacked on the first memory chip.

11. The semiconductor package of claim 8 , wherein the lower package further includes a bonding wire which connects the package substrate and the first terminal.

12. The semiconductor package of claim 8 , wherein the at least one dummy hole comprises a plurality of dummy holes, and
an arrangement of the dummy holes is non-uniform.

13. The semiconductor package of claim 8 , wherein an air gap exists between the upper package and the lower package.

14. A semiconductor package comprising:
a package substrate;
a plurality of microbumps disposed on the package substrate;
a flip chip stacked on the plurality of microbumps and electrically connected to the package substrate via the plurality of microbumps;
an underfill film which surrounds the plurality of microbumps between the flip chip and the package substrate;
an adhesive film on the flip chip;
an interposer which is stacked on the adhesive film and includes an interposer substrate and a first terminal and a second terminal on an upper surface of the interposer substrate;
a bonding wire which electrically connects the first terminal and the package substrate;
a mold layer which covers the interposer, the flip chip and the bonding wire,
wherein the mold layer has a signal hole therein which leads to and is open at the second terminal, and at least one dummy hole therein spaced apart from the signal hole and situated over the upper surface of the interposer; and
a protective film on the upper surface of the interposer and exposed by each of the at least one dummy hole.

15. The semiconductor package of claim 14 , wherein a dimension of the interposer in a horizontal direction parallel to the upper surface thereof is greater than a dimension of the flip chip in said horizontal direction.

16. The semiconductor package of claim 14 , further comprising:
a solder ball disposed inside the signal hole.

17. The semiconductor package of claim 16 , further comprising:
a memory package stacked on the solder ball.

18. The semiconductor package of claim 14 , wherein the at least one dummy hole comprises a plurality of dummy holes situated over the upper surface of the interposer.

19. The semiconductor package of claim 14 , wherein a thickness of the protective film and a thickness of the second terminal are the same.

20. The semiconductor package of claim 14 , wherein the first and second terminals are disposed on a first region of the upper surface of the interposer, and
the protective film is disposed on a second region of the upper surface of the interposer that is apart from the first region and is not disposed on the first region.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Young Bae

Classifications

• H10W74/129

  forming a chip-scale package [CSP] · CPC title

• H10W72/90

  Bond pads, in general · CPC title

• H10W74/10

  characterised by their shape or disposition · CPC title

• H10W70/60

  Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) · CPC title

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title