Printed circuit board and semiconductor package using the same

Patent metadata

Field	Value
Publication number	US-9502341-B2
Application number	US-201514640011-A
Country	US
Kind code	B2
Filing date	Mar 5, 2015
Priority date	Aug 14, 2014
Publication date	Nov 22, 2016
Grant date	Nov 22, 2016

Abstract

Embodiments of the inventive aspect include a printed circuit board and a semiconductor package using the same. The semiconductor package includes a substrate having one or more connection pads, semiconductor chips mounted on the substrate, an underfill layer filling a region between the semiconductor chips and the substrate, and solder bumps electrically connecting the connection pads and the semiconductor chips in the underfill layer. The substrate includes void preventing patterns protruding on a top surface of the substrate under the underfill layer.

First claim

What is claimed is:

1. A semiconductor package comprising:
a substrate including one or more connection pads;
semiconductor chips mounted on the substrate;
an underfill layer filling a region between the semiconductor chips and the substrate; and
solder bumps electrically connecting the connection pads and the semiconductor chips in the underfill layer,
wherein the substrate includes void preventing patterns protruding on a top surface of the substrate under the underfill layer, and
wherein the substrate includes a solder resist layer planarly formed on its surface and the void preventing patterns are formed on the solder resist layer.

2. The semiconductor package of claim 1 , wherein top surfaces of the void preventing patterns are not in contact with bottom surfaces of the semiconductor chips.

3. The semiconductor package of claim 1 , wherein the solder resist layer and the void preventing patterns include the same material.

4. The semiconductor package of claim 1 , wherein a top surface of the solder resist layer is higher than top surfaces of the connection pads.

5. The semiconductor package of claim 4 , wherein the top surfaces of the void preventing patterns are positioned higher than or at the same height with the top surface of the solder resist layer.

6. The semiconductor package of claim 1 , wherein the void preventing patterns have a height in a range of 3 micrometers (μm) to 30 μm.

7. The semiconductor package of claim 1 , wherein a region having the void preventing patterns is not overlapped with a region having the connection pads.

8. A semiconductor package comprising:
a substrate including first and second regions on a top surface of the substrate, the first and second regions not overlapping with each other;
a plurality of connection pads spaced apart from each other on the first region; and
void preventing patterns protruding on the second region of the top surface of the substrate,
wherein the void preventing patterns include bar patterns shaped of bars separated from each other by a predetermined distance.

9. The semiconductor package of claim 8 , further comprising semiconductor chips mounted on the substrate that overlap the first and second regions.

10. The semiconductor package of claim 9 , wherein the semiconductor chips include solder bumps disposed at bottom surfaces thereof to be brought into contact with the connection pads.

11. The semiconductor package of claim 8 , wherein the bar patterns extend in one direction in parallel with each other.

12. The semiconductor package of claim 8 , wherein at least some of the bar patterns include one or more trenches separating the bar patterns from each other.

13. A semiconductor package comprising:
a substrate including a plurality of connection pads in a first region;
one or more semiconductor chips;
a plurality of solder bumps electrically connecting the plurality of connection pads in the first region to the one or more semiconductor chips;
a second region between the substrate and the one or more semiconductor chips in which no connection pads and no solder bumps are disposed;
an underfill layer disposed between the substrate and the one or more semiconductor chips, the underfill layer encapsulating the plurality of solder bumps; and
a plurality of void preventing patterns disposed in the second region, the plurality of void preventing patterns configured to prevent a void in the underfill layer.

14. The semiconductor package of claim 13 , wherein:
the plurality of void preventing patterns include a plurality of bars in parallel with each other,
the plurality of bars are not in direct contact with the one or more semiconductor chips,
the plurality of bars extend in a dispensing direction of the underfill layer, and
the plurality of bars are arranged in parallel with the dispensing direction.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Song Jik-Ho
• Kim Ga-Young
• Kim Woo-Jae
• Ro Young-Hoon

Classifications

• H05K3/3436

  having an array of bottom contacts, e.g. pad grid array or ball grid array components · CPC title

• H05K1/00

  Printed circuits · CPC title

• H05K2203/0588

  Second resist used as pattern over first resist · CPC title

• H05K2201/10977

  Encapsulated connections · CPC title

• H05K2201/09909

  Special local insulating pattern, e.g. as dam around component · CPC title