Electrostatic discharge protection circuit

Patent metadata

Field	Value
Publication number	US-12463115-B2
Application number	US-202418442671-A
Country	US
Kind code	B2
Filing date	Feb 15, 2024
Priority date	Nov 23, 2020
Publication date	Nov 4, 2025
Grant date	Nov 4, 2025

Abstract

An electrostatic discharge protection circuit includes: a first electrostatic discharge protection device structure; a first contact pad above the first electrostatic discharge protection device structure in a cross-sectional view; and below the first electrostatic discharge protection device structure in the cross-sectional view, a metal connection coupling the first electrostatic discharge protection device structure to a second contact pad remote from the first contact pad, wherein the metal connection in the cross-sectional view only partially overlaps the first electrostatic discharge protection device structure.

First claim

What is claimed is:

1 . An electrostatic discharge protection circuit, comprising:
a first electrostatic discharge protection device structure; a first contact pad above the first electrostatic discharge protection device structure in a cross-sectional view; and below the first electrostatic discharge protection device structure in the cross-sectional view, a metal connection coupling the first electrostatic discharge protection device structure to a second contact pad remote from the first contact pad, wherein the metal connection in the cross-sectional view only partially overlaps the first electrostatic discharge protection device structure, wherein the first electrostatic discharge protection device structure is laterally surrounded by a dielectric material, wherein at least part of the second contact pad is uncovered by a hole in the dielectric material, wherein the metal connection contacts the second contact pad through the hole in the dielectric material, wherein the first contact pad and the second contact pad are each a metal pad.

2 . The circuit of claim 1 , further comprising a molded carrier.

3 . The circuit of claim 1 , wherein the first electrostatic discharge protection device structure comprises one or more doped layers adjacent to the first contact pad.

4 . The circuit of claim 1 , wherein the first electrostatic discharge protection device structure is formed in a first area on a front side of a semiconductor substrate, wherein the second contact pad is formed in a second area on the front side of the semiconductor substrate, and wherein the metal connection connects the first electrostatic discharge protection device structure to the second area.

5 . The circuit of claim 4 , further comprising a carrier at a back side of the semiconductor substrate.

6 . The circuit of claim 5 , wherein the carrier is molded on the back side of the semiconductor substrate.

7 . The circuit of claim 4 , wherein a space between the first area and the second area is filled by the dielectric material.

8 . The circuit of claim 4 , wherein the metal connection is partly covered by the dielectric material.

9 . The circuit of claim 1 , wherein the first electrostatic discharge protection device structure comprises a Zener diode structure.

10 . The circuit of claim 1 , further comprising a passivation layer covering the metal connection such that the metal connection is sandwiched between the dielectric material and the passivation layer.

11 . The circuit of claim 10 , further comprising a mold compound layer covering the passivation layer such that the passivation layer is sandwiched between the dielectric material and the mold compound layer.

Assignees

• Infineon Technologies Ag

Inventors

• Schmenn Andre
• Diefenbeck Klaus
• Willemen Joost Adriaan

Classifications

• H10W74/01

  Manufacture or treatment · CPC title

• H10W20/40 Primary

  Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes · CPC title

• H10D89/611

  using diodes as protective elements · CPC title

• H10D89/921 Primary

  characterised by the configuration of the interconnections connecting the protective arrangements, e.g. ESD buses · CPC title

• H10D84/038

  using silicon technology, e.g. SiGe · CPC title