Method for etching high aspect ratio structures

Patent metadata

Field	Value
Publication number	US-12463053-B2
Application number	US-202318193455-A
Country	US
Kind code	B2
Filing date	Mar 30, 2023
Priority date	Mar 30, 2023
Publication date	Nov 4, 2025
Grant date	Nov 4, 2025

Abstract

A method and system for etching high aspect ratio structures in a semiconducting processing chamber are disclosed herein. In one example, a method of patterning a substrate comprises etching the substrate to form a recess, depositing a passivation layer on sidewalls of the recess, treating the passivation layer, and etching the recess to a second depth. The substrate etch forms a recess to a first depth, the substrate having a mask layer disposed thereon. The treating of the passivation layer is for removal of a clogging material formed from an etch byproduct on the mask layer. The etching the recess to a second depth while maintaining a minimum variation of a recess sidewall width.

First claim

What is claimed is:

1 . A method of patterning a substrate comprising:
(a) etching a substrate with a first etchant to form a recess to a first depth within the substrate, the substrate having a mask layer disposed thereon, wherein an etch byproduct from the substrate forms a clogging material at a top of the recess; (b) depositing a passivation layer on the clogging material and sidewalls of the recess; (c) performing a second etch operation with a second etchant on the passivation layer to remove the clogging material formed from the etch byproduct on the mask layer; and (d) etching with the first etchant the recess to a second depth.

2 . The method of claim 1 , wherein the first depth is about 2 nanometers to about 300 nanometers.

3 . The method of claim 2 , wherein the first depth is about 200 nanometers.

4 . The method of claim 1 , wherein depositing the passivation layer comprises exposing the substrate to a plasma formed from an oxygen containing precursor gas.

5 . The method of claim 1 , wherein depositing the passivation layer further comprises generating an oxygen plasma with about 2,500 W RF power and about 100 W bias power at about 13.56 MHz.

6 . The method of claim 1 , wherein treating the passivation layer comprises exposing a sidewall of the mask layer.

7 . The method of claim 1 , wherein the substrate comprises a plurality of silicon layers or alternating silicon and silicon germanium layers.

8 . The method of claim 1 , wherein the treating the passivation layer further comprises generating a plasma from a gas mixture of NF 3 , Ar, and O 2 under a pressure of about 20 milliTorr to about 60 milliTorr.

9 . The method of claim 8 , wherein the treating the passivation layer further comprises exposing the substrate for a duration of about 10 seconds to about 100 seconds.

10 . The method of claim 1 , where in etching a substrate further comprises generating a plasma from a gas mixture comprising Cl 2 , HBr, and O 2 .

11 . The method of claim 10 , wherein generating a plasma uses a 4,000 watts to about 4,500 watts bias power.

12 . The method of claim 1 , where in etching the recess further comprises generating a plasma from a gas mixture comprising Cl 2 , HBr, and O 2 .

13 . The method of claim 12 , wherein generating a plasma uses a 4,000 watts to about 4,500 watts bias power.

14 . The method of claim 1 , wherein (a), (b), (c), and (d) are repeated until the recess has an aspect ratio of at least 100:1.

15 . The method of claim 1 , wherein maintaining a minimum variation of a recess sidewall width comprises maintaining the variation to within about 10 nanometers.

16 . A method of patterning a substrate comprising:
(a) etching a substrate to remove a thin layer of oxidation to expose a silicon containing film stack; (b) etching the substrate to form a recess to a first depth within the film stack, the substrate comprising a mask layer disposed above the film stack, the mask layer having inner sidewalls, wherein an etch byproduct from the substrate forms a clogging material at a top of the recess, wherein etching the substrate comprises:
generating a plasma from a gas mixture of Cl 2 , HBr, O 2 , and Ar; and
exposing the substrate to the plasma for about 10 seconds to about 200 seconds;
(c) oxidizing the etch byproduct, the sidewalls of the recess and the inner sidewalls of the mask layer by exposing the substrate to a generated oxygen plasma for about 10 seconds to about 20 seconds, the mask layer inner sidewalls having the etch byproduct, wherein the etch byproduct is silicon-containing; (d) exposing the mask layer sidewalls by a controlled etch removing the etch byproduct, the controlled etch comprising:
generating a plasma from a gas mixture of NF 3 , Ar, and O 2 ; and
exposing the substrate to the plasma for about 10 seconds to about 200 seconds;
(e) repeating (b), (c), (d); and (f) etching the recess to a final depth while maintaining vertical profile of the first depth to within 5 nanometers of a center of the recess, etching the recess to a second depth.

17 . The method of claim 16 , wherein the final depth is a 100:1 aspect ratio structure.

Assignees

• Applied Materials Inc

Inventors

• Qiao Feng
• Zhou Hailong
• Fu Qian
• Park Sangjun
• Choi Jayoung
• Agarwal Radhe
• Liu Tong

Classifications

• H10P50/242

  of Group IV materials · CPC title

• H10P50/71 Primary

  using masks for conductive or resistive materials · CPC title

• H10P50/268 Primary

  of silicon-containing layers · CPC title

• H10P50/283

  by chemical means · CPC title

• H01L21/32139

  Electricity · mapped topic