Displaying base plate and manufacturing method thereof, and displaying device

Patent metadata

Field	Value
Publication number	US-12457803-B2
Application number	US-202117772761-A
Country	US
Kind code	B2
Filing date	Jun 29, 2021
Priority date	Jun 29, 2021
Publication date	Oct 28, 2025
Grant date	Oct 28, 2025

Abstract

Disclosed are a thin film transistor and a manufacturing method therefor, a displaying base plate and a displaying apparatus. The thin film transistor includes an active layer, a first insulating layer and a gate layer which are disposed in stack, wherein the active layer includes a source contact area, a drain contact area, and a channel area connecting the source contact area and the drain contact area; the channel area includes a first channel area, a first resistance area and a second channel area sequentially disposed in a first direction; the gate layer includes a first gate and a second gate which are separately disposed; an orthographic projection of the first gate on a plane where the active layer is located covers the first channel area; and an orthographic projection of the second gate on a plane where the active layer is located covers the second channel area.

First claim

The invention claimed is:

1. A displaying base plate, comprising a substrate and a first thin film transistor disposed on one side of the substrate, the thin film transistor comprising an active layer, a first insulating layer, and a gate layer which are disposed in stack, wherein
the active layer comprises a source contact area, a drain contact area, and a channel area connecting the source contact area and the drain contact area; the channel area comprises a first channel area, a first resistance area and a second channel area sequentially disposed in a first direction,
the gate layer comprises a first gate and a second gate which are separately disposed; an orthographic projection of the first gate on a plane where the active layer is located covers the first channel area, and an orthographic projection of the second gate on a plane where the active layer is located covers the second channel area,
the displaying base plate comprises an active area and a non-active area located at the periphery of the active area, and the first thin film transistor is located in the active area,
the active area further comprises a data line and scan lines, which are disposed on one side of the substrate that is close to the first thin film transistor; the data line extends in the first direction, the scan lines comprise a first scan line and a second scan line, the first gate extends in a second direction intersecting with the first direction to form the first scan line, the second gate extends in the second direction to form the second scan line, the source contact area is connected to the data line; and an orthographic projection of the channel area on the substrate is located in an orthographic projection range of the data line on the substrate,
the active layer is located on one side of the gate layer that is close to the substrate, a second insulating layer is disposed on one side of the gate layer that is away from the substrate, a drain of the first thin film transistor is disposed on one side of the second insulating layer that is away from the substrate plate, the drain and the drain contact area are connected through via holes formed in the second insulating layer and the first insulating layer, and the drain is also connected to a first transparent electrode layer,
a third insulating layer is disposed on one side of the first transparent electrode layer that is away from the substrate; a second transparent electrode layer is disposed on one side of the third insulating layer that is away from the substrate, the second transparent electrode layer is connected to a first fixed potential input terminal, and an overlap exists between an orthographic projection of the second transparent electrode layer on the substrate and the orthographic projection of the first transparent electrode layer on the substrate,
a fourth insulating layer is disposed on one side of the second transparent electrode layer that is away from the substrate; the data line is disposed on one side of the fourth insulating layer that is away from the substrate plate, and the data line and the source contact area are connected through via holes formed in the fourth insulating layer, the third insulating layer, the second insulating layer and the first insulating layer,
the first transparent electrode layer comprises a first transfer electrode and a second transfer electrode that are integrally formed, the first transfer electrode is connected to the drain, an orthographic projection of the second transfer electrode on the substrate is located in an orthographic projection range of the first scan line, the second scan line, and an area between the first scan line and the second scan line on the substrate,
a first planarization layer is disposed on one side of the data line that is away from the substrate, and a through hole is formed in the first planarization layer, the through hole penetrates through the first planarization layer, the fourth insulating layer and the third insulating layer, to expose the second transfer electrode, and
a third transparent electrode layer, a second planarization layer and a pixel electrode layer are disposed in stack on one side of the first planarization layer that is away from the substrate, wherein the third transparent electrode layer is disposed close to the substrate, an orthographic projection of the third transparent electrode layer on the substrate covers an orthographic projection of the through hole on the substrate, the third transparent electrode layer is configured to connect the pixel electrode layer and the second transfer electrode, and the second planarization layer is configured to planarize the through hole.

2. The displaying base plate according to claim 1 , wherein a material of the drain is a metal, an orthographic projection of the drain on the substrate and an orthographic projection of the drain contact area on the substrate are located in the orthographic projection range of the data line on the substrate, and the first transparent electrode layer is disposed on one side of the drain that is away from the substrate.

3. The displaying base plate according to claim 1 , further comprising a source disposed in the same layer as the drain, the data line and the source are connected through the via holes formed in the fourth insulating layer and the third insulating layer, the source and the source contact area are connected through the via holes formed in the second insulating layer and the first insulating layer, a material of the source is a metal, and an orthographic projection of the source on the substrate and an orthographic projection of the source contact area on the substrate are located in the orthographic projection range of the data line on the substrate.

4. The displaying base plate according to claim 1 , wherein a fifth insulating layer and a common electrode layer are disposed in stack on one side of the pixel electrode layer that is away from the substrate, the fifth insulating layer is disposed close to the substrate, the common electrode layer comprises a plurality of strip electrodes, and a material of the common electrode layer is a metal.

5. The displaying base plate according to claim 1 , wherein the active area comprises an opening area and a non-opening area, a material of the active layer comprises polycrystalline silicon, a buffer layer is further displayed between the substrate and the active layer; and
an overlap exists between an orthographic projection of an inorganic film layer disposed on one side of the substrate that is close to the first thin film transistor on the substrate and the opening area; and the inorganic film layer comprises at least one of the following film layers: the buffer layer, the first insulating layer, and the second insulating layer.

6. The displaying base plate according to claim 5 , wherein an overlap exists between an orthographic projection of the second transparent electrode layer on the substrate and the opening area; and
an overlap exists between an orthographic projection of the first transparent electrode layer on the substrate and the opening area.

7. The displaying base plate according to claim 5 , wherein a second thin film transistor is disposed on one side of the buffer layer that is away from the substrate, the second thin film transistor is located in the non-active area, and a material of an active layer of the second thin film transistor comprises polycrystalline silicon.

8. The displaying base plate according to claim 1 , wherein a shielding layer is further disposed between the substrate and the active layer, and an orthographic projection of the shielding layer on the substrate covers an orthographic projection of the channel area on the substrate.

9. A di

Assignees

• Boe Technology Group Co Ltd
• Beijing Boe Technology Dev Co Ltd

Inventors

• Li Fuqiang
• Zhang Zhen
• Zhang Zhenyu
• Wang Lizhong
• Ning ce
• Di Yunping
• Fang Zheng
• Han Jiahui
• Zhang Chenyang
• Wang Yawei
• Xu Chengfu

Classifications

• H10D86/421

  having a particular composition, shape or crystalline structure of the active layer · CPC title

• H10D86/0231

  using masks, e.g. half-tone masks · CPC title

• H10D86/451

  characterised by the compositions or shapes of the interlayer dielectrics · CPC title

• H10D30/674

  characterised by the active materials · CPC title

• H10D30/6757

  characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title