Array substrate, manufacturing method thereof and display device

Patent metadata

Field	Value
Publication number	US-9917198-B2
Application number	US-201514769765-A
Country	US
Kind code	B2
Filing date	Feb 12, 2015
Priority date	Oct 22, 2014
Publication date	Mar 13, 2018
Grant date	Mar 13, 2018

Abstract

The present disclosure provides an array substrate, a manufacturing method thereof and a display device. The array substrate includes an active layer, a gate insulating layer and a gate electrode layer formed sequentially on a base substrate. The active layer includes a first heavily-doped region, a first lightly-doped region, a first non-doped region, a second lightly-doped region, a second non-doped region, a third lightly-doped region and a second heavily-doped region which are sequentially arranged in a horizontal direction.

First claim

What is claimed is:

1. An array substrate, comprising a base substrate, an active layer, a gate insulating layer and a gate electrode layer formed sequentially on the base substrate; wherein the active layer comprises a first heavily-doped region, a first lightly-doped region, a first non-doped region, a second lightly-doped region, a second non-doped region, a third lightly-doped region and a second heavily-doped region which are sequentially arranged in a horizontal direction;
wherein a projection of a pattern of the gate electrode layer onto the array substrate covers projections of the first lightly-doped region, the first non-doped region, the second lightly-doped region, the second non-doped region and the third lightly-doped region onto the array substrate; and
wherein the projection of the pattern of the gate electrode layer onto the array substrate only covers the projections of the first lightly-doped region, the first non-doped region, the second lightly-doped region, the second non-doped region and the third lightly-doped region onto the array substrate.

2. The array substrate according to claim 1 , wherein the second lightly-doped region is arranged in a middle of the active layer in the horizontal direction.

3. The array substrate according to claim 1 , further comprising a first insulating layer arranged between the base substrate and the active layer.

4. The array substrate according to claim 1 , further comprising:
a second insulating layer arranged on the gate insulating layer and the gate electrode layer;
a source-drain electrode layer arranged on the second insulating layer; wherein the source-drain electrode layer comprises a source electrode line and a drain electrode line, the source-drain electrode layer is electrically connected to the first heavily-doped region through a first via-hole passing through the second insulating layer and the gate insulating layer, and the drain electrode line is electrically connected to the second heavily-doped region through a second via-hole passing through the second insulating layer and the gate insulating layer;
a passivation layer arranged on the source-drain electrode layer; and
a pixel electrode layer arranged on the passivation layer and electrically connected to the drain electrode line through a third via-hole in the passivation layer.

5. The array substrate according to claim 4 , further comprising a protection layer arranged on the passivation layer and the pixel electrode layer, and a common electrode layer arranged on the protection layer.

6. The array substrate according to claim 1 , wherein the first lightly-doped region, the second lightly-doped region and the third lightly-doped region are each of a length of 1 μm to 3 μm; and an ion injection concentration for each of the first lightly-doped region, the second lightly-doped region and the third lightly-doped region is 5×10 11 ions/cm 2 to 1×10 14 ions/cm 2 .

7. The array substrate according to claim 1 , wherein an ion injection concentration for each of the first heavily-doped region and the second heavily-doped region is 1×10 14 ions/cm 2 to 1.5×10 20 ions/cm 2 ; and the first heavily-doped region and the second heavily-doped region are each of a length of 2 μm to 5 μm.

8. A display device comprising the array substrate according to claim 1 .

9. A method for manufacturing an array substrate, comprising:
forming patterns of an active layer, a gate insulating layer and a gate electrode layer sequentially on a base substrate; wherein the active layer comprises a first heavily-doped region, a first lightly-doped region, a first non-doped region, a second lightly-doped region, a second non-doped region, a third lightly-doped region and a second heavily-doped region which are sequentially arranged in a horizontal direction;
wherein the step of forming the patterns of the active layer, the gate insulating layer and the gate electrode layer sequentially on the base substrate comprises:
depositing an a-Si film onto the base substrate, and after the a-Si film is crystallized, forming silicon islands of the active layer by a patterning process;
applying a photoresist onto the silicon islands, and forming a plurality of gaps in the photoresist by a patterning process in such a manner that the plurality of gaps are located above positions in the silicon islands where the first lightly-doped region, the second lightly-doped region and the third lightly-doped region are located, respectively;
injecting ions at the positions in the silicon islands where the first lightly-doped region, the second lightly-doped region and the third lightly-doped region are located, respectively, through the plurality of gaps, thereby forming the first lightly-doped region, the second lightly-doped region and the third lightly-doped region of the active layer;
depositing a gate insulating layer film and a gate electrode layer film sequentially onto the silicon islands, and forming the patterns of the gate insulating layer and the gate electrode layer by a patterning process;
wherein a projection of the pattern of the gate electrode layer onto the array substrate covers projections of the first lightly-doped region, the first non-doped region, the second lightly-doped region, the second non-doped region and the third lightly-doped region onto the array substrate, and wherein the projection of the pattern of the gate electrode layer onto the array substrate only covers the projections of the first lightly-doped region, the first non-doped region, the second lightly-doped region, the second non-doped region and the third lightly-doped region onto the array substrate; and
injecting ions at positions in the silicon islands where the first heavily-doped region and the second heavily-doped region are located, respectively, thereby forming the first heavily-doped region and the second heavily-doped region of the active layer.

10. The method according to claim 9 , wherein the second lightly-doped region is arranged in a middle of the active layer in the horizontal direction.

11. The method according to claim 9 , wherein before the step of forming the patterns of the active layer, the gate insulating layer and the gate electrode layer sequentially onto the base substrate, the method further comprises: forming a pattern of a first insulating layer on the base substrate, the pattern of the active layer being arranged on the first insulating layer.

12. The method according to claim 9 , further comprising:
forming a pattern of a second insulating layer on the gate insulating layer and the gate electrode layer;
forming a first via-hole and a second via-hole in the second insulating layer and the gate insulating layer in such a manner that the first via-hole is located above the first heavily-doped region and the second via-hole is located above the second heavily-doped region;
forming a source-drain electrode layer on the second insulating layer in such a manner that the source-drain electrode layer comprises a source electrode line electrically connected to the first heavily-doped region through the first via-hole, and a drain electrode line electrically connected to the second heavily-doped region through the second via-hole;
forming a pattern of a passivation layer on the source-drain electrode layer in such a manner that the pattern of the passivation layer is provided with a third via-hole; and
forming a pattern of a pixel electrode layer on the passivation layer in such a manner that the pixel electrode layer is electrically connected to the drain electrode line through the third via-hole.

13. The method according to claim 12 , further comprising:
forming a p

Assignees

• Boe Technology Group Co Ltd
• Beijing Boe Optoelectronics Tech Co Ltd

Inventors

• Xie Zhenyu

Classifications

• H01L29/78618

  Electricity · mapped topic

• H01L29/0615

  Electricity · mapped topic

• H01L29/78621

  Electricity · mapped topic

• H01L29/78696

  Electricity · mapped topic

• H01L29/1041

  Electricity · mapped topic