Array substrate and its manufacturing method, display device

Patent metadata

Field	Value
Publication number	US-2016254283-A1
Application number	US-201514769577-A
Country	US
Kind code	A1
Filing date	Apr 17, 2015
Priority date	Sep 30, 2014
Publication date	Sep 1, 2016
Grant date	—

Abstract

An array substrate includes a base substrate ( 10 ) and a gate line ( 11 ) and a data line ( 12 ) provided on the base, the gate line ( 11 ) and the data line ( 12 ) define a pixel unit, and in the pixel unit, a thin film transistor ( 13 ) is provided, the thin film transistor ( 13 ) includes a gate electrode ( 131 ), a gate insulation layer ( 132 ), an active layer ( 133 ), a source electrode ( 134 ) and a drain electrode ( 135 ). The gate insulation layer ( 132 ) includes a first gate insulation portion ( 1321 ) and a second gate insulation portion ( 1322 ), the gate electrode ( 131 ) is located between the first gate insulation portion ( 1321 ) and the second gate insulation portion ( 1322 ), and the second gate insulation portion ( 1322 ) is located between the gate electrode ( 131 ) and the active layer ( 133 ). The array substrate further includes a conductive pad ( 114 ), and a first via ( 15 ) corresponding to the conductive pad ( 114 ) is provided in the gate insulation layer ( 132 ) at both sides of the gate line ( 11 ), and the data line ( 12 ) is connected to the conductive pad ( 114 ) through the first via ( 15 ). The array substrate is capable of improving the definition, the resolution and the aperture ratio of a display device. A manufacturing method for an array substrate and a display device including such an array substrate are also disclosed.

First claim

1 . An array substrate comprising:
a base substrate, and a gate line and a data line which are provided on the base substrate to be intersected with each other, wherein the gate line and the data line define a pixel unit, the pixel unit is provided with a thin film transistor therein, the thin film transistor includes a gate electrode, a gate insulation layer, an active layer, a source electrode and a drain electrode, the gate insulation layer includes a first gate insulation portion and a second gate insulation portion, the gate electrode is located between the first gate insulation portion and the second gate insulation portion, the second gate insulation portion is located between the gate electrode and the active layer; a conductive pad located at an intersection position of the gate line and the data line; and a first via corresponding to the conductive pad provided in the gate insulation layer at both sides of the gate line, wherein the data line is connected to the conductive pad through the first via.

2 . The array substrate according to claim 1 , wherein:
along a direction perpendicular to the gate line, the conductive pad has a size larger than that of the gate line.

3 . The array substrate according to claim 1 , wherein:
at the thin film transistor, the first gate insulation portion, the gate electrode, the second gate insulation portion, the active layer, the source electrode and the drain electrode provided at a same layer are subsequently provided on the base substrate in a direction away from the base substrate; at the intersection position between the gate line and the data line, the conductive pad, the first gate insulation portion, the gate line, the second gate insulation portion and the data line are subsequently provided on the base substrate in the direction away from the base substrate.

4 . The array substrate according to claim 1 , wherein:
at the thin film transistor, the source electrode and the drain electrode provided at a same layer, the active layer, the second gate insulation portion, the gate electrode, the first gate insulation portion are subsequently provided on the base substrate in a direction away from the base substrate, and the data line is connected to the source electrode via a second via in the gate insulation layer; at the intersection position between the gate line and the data line, the conductive pad, the second gate insulation portion, the gate line, the first gate insulation portion and the data line are subsequently provided on the base substrate.

5 . The array substrate according to claim 1 , wherein the second gate insulation portion has a dielectric constant larger than that of the first gate insulation portion.

6 . The array substrate according to claim 5 , wherein the first gate insulation portion has a thickness of 1000 Ř3000 Å, and the second gate insulation portion has a thickness of 1000 Ř3000 Å.

7 . A display device including the array substrate according to claim 1 .

8 . A manufacturing method for an array substrate comprising:
forming a gate line, a gate electrode, a gate insulation layer, an active layer, a data line, a source electrode, a drain electrode and a conductive pad on a base substrate, wherein the gate insulation layer includes a first gate insulation portion and a second gate insulation portion; the gate electrode is located between the first gate insulation portion and the second gate insulation portion, and the second gate insulation portion is located between the gate electrode and the active layer; the conductive pad is located at an intersection position between the gate line and the data line, and a first via corresponding to the conductive pad is formed in the gate insulation layer at both sides of the gate line, and the data line is connected to the conductive pad through the first via.

9 . The manufacturing method for the array substrate according to claim 8 , wherein:
a conductive pad metal layer is formed on the base substrate, and after subjected from patterning process, a pattern including the conductive pad is formed; on the base substrate on which the pattern including the conductive pad has been formed, the first gate insulation portion is formed; on the base substrate on which the first gate insulation portion has been formed, a gate metal layer is formed, and after subjected from patterning process, a pattern including the gate line and the gate electrode is formed; on the base substrate on which the pattern including the gate line and the gate electrode has been formed, a second gate insulation film is formed, and after subjected from patterning process, the second gate insulation portion is formed; on the base substrate on which the second gate insulation portion has been formed, a semiconductor layer is formed, and after subjected from patterning process, a pattern including the active layer is formed; by performing patterning process, the first via corresponding to the conductive pad is formed in the gate insulation layer at both sides of each of the gate line; on the base substrate on which the first via has been formed, a source/drain metal layer is formed, and after subjected from patterning process, a pattern including the data line, the source electrode and the drain electrode is formed, wherein the data line and the gate line are intersected above the conductive pad, and the data line is connected to the conductive pad through the first via.

10 . The manufacturing method for the array substrate according to claim 8 , wherein:
a source/drain metal layer is formed on the base substrate, and after subjected from patterning process, a pattern including the source electrode, the drain electrode and the conductive pad is formed; on the base substrate on which the pattern including the source electrode, the drain electrode and the conductive pad has been formed, a semiconductor layer is formed, and after subjected from patterning process, a pattern including the active layer is formed; on the base substrate on which the pattern including the active layer has been formed, a second gate insulation film is formed, and after subjected from patterning process, the second gate insulation portion is formed; on the base substrate on which the second gate insulation portion has been formed, a gate metal layer is formed, and after subjected from patterning process, a pattern including the gate line and the gate electrode is formed; on the base substrate on which the pattern including the gate line and the gate electrode has been formed, the first gate insulation portion is formed; after subjected from patterning process, the first via corresponding to the conductive pad and the second via corresponding to the source electrode are formed in the gate insulation layer; on the gate insulation layer in which the first via and the second via have been formed, a data metal layer is formed, and after subjected from patterning process, a pattern including the data line is formed, the data line is connected with the conductive pad through the first via, and connected to the source electrode through the second via.

11 . The manufacturing method for the array substrate according to claim 9 , wherein:
the first gate insulation portion and the second gate insulation film are formed by deposition, and processing parameters for depositing the second gate insulation film are different from processing parameter for depositing the first gate insulation portion, so that the second gate insulation portion formed after subjected from patterning processing has a dielectric constant larger than that of the first gate insulation portion.

12 . The array substrate according to claim

Assignees

• Boe Technology Group Co Ltd
• Hefei Boe Optoelectronics Tech

Inventors

• Shen Qiyu

Classifications

• H10D84/01

  Manufacture or treatment · CPC title

• H10D86/471

  having different architectures, e.g. having both top-gate and bottom-gate TFTs · CPC title

• H10D86/451

  characterised by the compositions or shapes of the interlayer dielectrics · CPC title

• H10D86/441

  Interconnections, e.g. scanning lines · CPC title

• H10D86/0212

  comprising manufacture, treatment or coating of substrates · CPC title