Nonvolatile memory device and operating method of the same

Patent metadata

Field	Value
Publication number	US-12457754-B2
Application number	US-202318169436-A
Country	US
Kind code	B2
Filing date	Feb 15, 2023
Priority date	Aug 16, 2022
Publication date	Oct 28, 2025
Grant date	Oct 28, 2025

Abstract

Provided are a nonvolatile memory device and an operating method thereof. The nonvolatile memory device may include a conductive pillar, a resistance change layer surrounding a side surface of the conductive pillar, a semiconductor layer surrounding a side surface of the resistance change layer, a gate insulating layer surrounding a side surface of the semiconductor layer, and a plurality of insulating patterns and a plurality of gate electrodes alternately arranged along a surface of the gate insulating layer. The plurality of insulating patterns and the plurality of gate electrodes may surround a side surface of the gate insulating layer.

First claim

What is claimed is:

1. A nonvolatile memory device comprising:
a conductive pillar;
a resistance change layer surrounding a side surface of the conductive pillar;
a semiconductor layer surrounding a side surface of the resistance change layer;
a gate insulating layer surrounding a side surface of the semiconductor layer;
a plurality of insulating patterns and a plurality of gate electrodes, the plurality of insulating patterns and the plurality of gate electrodes being alternately arranged along a surface of the gate insulating layer, and the plurality of insulating patterns and the plurality of gate electrodes surrounding a side surface of the gate insulating layer;
a second bit line electrically connected to the conductive pillar, the second bit line being configured to provide a first voltage to the conductive pillar; and
a first bit line electrically insulated from the second bit line, the first bit line being electrically connected to the semiconductor layer, and the first bit line being configured to provide a second voltage to the semiconductor layer.

2. The nonvolatile memory device of claim 1 , wherein the first voltage and the second voltage are different from each other.

3. The nonvolatile memory device of claim 1 , wherein the first voltage is greater than the second voltage.

4. The nonvolatile memory device of claim 1 , wherein a difference between the first voltage and the second voltage is less than an absolute value of the second voltage.

5. The nonvolatile memory device of claim 1 , wherein an absolute value of the second voltage is about 5 V or less.

6. The nonvolatile memory device of claim 1 , further comprising:
a controller, wherein
the controller is configured to apply a turn-off voltage to a gate electrode corresponding to a selection memory cell in the plurality of gate electrodes, and
the controller is configured to apply a turn-on voltage to a gate electrode corresponding to a non-selection memory cell in the plurality of gate electrodes.

7. The nonvolatile memory device of claim 6 , wherein the turn-off voltage is less than at least one of the first voltage and the second voltage.

8. The nonvolatile memory device of claim 6 , wherein the turn-on voltage is greater than at least one of the first voltage and the second voltage.

9. The nonvolatile memory device of claim 6 , wherein a difference between the first voltage and the second voltage is less than a difference between the turn-on voltage and the turn-off voltage.

10. The nonvolatile memory device of claim 1 , wherein all regions of the conductive pillar are spatially spaced apart from all regions of the semiconductor layer.

11. The nonvolatile memory device of claim 1 , further comprising:
an insulating layer between the resistance change layer and the conductive pillar.

12. The nonvolatile memory device of claim 1 , further comprising:
an insulating layer in the conductive pillar.

13. The nonvolatile memory device of claim 12 , wherein
the insulating layer in the conductive pillar is in contact with the resistance change layer.

14. An operating method of a nonvolatile memory device, the nonvolatile memory device including a conductive pillar and a memory cell array along a side of the conductive pillar, the operating method comprising:
applying a turn-off voltage to a selection memory cell in the memory cell array;
applying a turn-on voltage to a non-selection memory cell in the memory cell array; and
during an operation on the selection memory cell, applying a first voltage to the conductive pillar and applying a second voltage to the memory cell array, the second voltage being different from the first voltage, wherein
a difference between the first voltage and the second voltage is less than an absolute value of the second voltage.

15. The operating method of claim 14 , wherein the first voltage is greater than the second voltage.

16. The operating method of claim 14 ,
wherein the difference between the first voltage and the second voltage is less than a difference between the turn-on voltage and the turn-off voltage.

17. The operating method of claim 14 , wherein the absolute value of the second voltage is about 5 V or less.

18. The operating method of claim 14 , wherein the turn-off voltage is less than at least one of the first voltage and the second voltage.

19. The operating method of claim 14 , wherein the turn-on voltage is greater than at least one of the first voltage and the second voltage.

20. An operating method of a nonvolatile memory device, the nonvolatile memory device including a conductive pillar and a memory cell array along a side of the conductive pillar, the operating method comprising:
applying a turn-off voltage to a selection memory cell in the memory cell array;
applying a turn-on voltage to a non-selection memory cell in the memory cell array; and
during an operation on the selection memory cell, applying a first voltage to the conductive pillar and applying a second voltage to the memory cell array, the second voltage being different from the first voltage,
wherein a difference between the first voltage and the second voltage is less than a difference between the turn-on voltage and the turn-off voltage.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Yumin
• Kang Jooheon
• Kim Sunho
• Kim Seyun
• Park Garam
• Song Hyunjae
• Ahn Dongho
• Yang Seungyeul
• Woo Myunghun
• Lee Jinwoo

Classifications

• G11C2213/79

  Array wherein the access device being a transistor · CPC title

• G11C2213/75

  Array having a NAND structure comprising, for example, memory cells in series or memory elements in series, a memory element being a memory cell in parallel with an access transistor · CPC title

• G11C2213/71

  Three dimensional array · CPC title

• G11C13/003

  Cell access · CPC title

• G11C13/0007

  comprising metal oxide memory material, e.g. perovskites · CPC title