Continuous time linear equalizers (CTLEs) of data interfaces

Patent metadata

Field	Value
Publication number	US-12456977-B2
Application number	US-202217885483-A
Country	US
Kind code	B2
Filing date	Aug 10, 2022
Priority date	Aug 10, 2022
Publication date	Oct 28, 2025
Grant date	Oct 28, 2025

Abstract

An electronic device (e.g., a CTLE circuit of a receiver of a data link) includes a current source and two differential transistor groups. The current source is configured to generate a bias current according to a data rate of data carried by a pair of differential input signals. A subset of the two differential transistor groups is configured to be driven by the bias current to generate a pair of differential output signals from the pair of differential input signals. The two differential transistor groups include a first plurality of transistors receiving a first input signal and a second plurality of transistors receiving a second input signal. The first and second input signals form the pair of differential input signals. In some implementations, each transistor is coupled to a biasing circuit including a DC path coupled to an adjustable biasing voltage level for selecting and deselecting the respective transistor.

First claim

What is claimed is:

1 . An electronic device, comprising:
a current source configured to generate a bias current in accordance with a data rate of data carried by a pair of differential input signals; two differential transistor groups coupled to the current source, wherein:
a subset of the two differential transistor groups is configured to be driven by the bias current to generate a pair of differential output signals from the pair of differential input signals; and
the two differential transistor groups include a first plurality of transistors configured to receive a first input signal and a second plurality of transistors configured to receive a second input signal, and the first and second input signals form the pair of differential input signals; and
a controller configured to generate a multibit control signal enabling multiple distinct levels for the bias current according to the data rate of the data carried by the pair of differential input signals, the control signal being distinct from the pair of differential input signals, wherein the control signal is configured to select the subset of the two differential transistor groups proportional to the bias current, such that each of the first plurality of transistors and the second plurality of transistors in the two differential transistor groups maintains substantially constant DC operating points independently of the data rate to ensure consistent performance of the two differential transistor groups.

2 . The electronic device of claim 1 , wherein:
sources of the first plurality of transistors are coupled to each other and to the current source, and drains of the first plurality of transistors are coupled to each other; and sources of the second plurality of transistors are coupled to each other and to the current source, and drains of the second plurality of transistors are coupled to each other.

3 . The electronic device of claim 1 , wherein:
the current source includes a plurality of current source components; each current source component is configured to provide a respective bias current portion; each of the first plurality of transistors and the second plurality of transistors is coupled with a respective current source component; and drains of the first plurality of transistors are coupled to each other, and drains of the second plurality of transistors are coupled to each other.

4 . The electronic device of claim 1 , wherein:
the first plurality of transistors include a first number of transistors; the second plurality of transistors include a second number of transistors, the second number equal to the first number; and each of the first plurality of transistors corresponds to and has a same size of a respective distinct one of the second plurality of transistors.

5 . The electronic device of claim 4 , wherein each of the first plurality of transistors and the second plurality of transistors has a predefined transistor size, and a subset of the first plurality of transistors are selected, such that a total size of the selected subset of the first plurality of transistors matches the bias current and the data rate.

6 . The electronic device of claim 4 , wherein each of the first plurality of transistors has a respective distinct transistor size.

7 . The electronic device of claim 6 , wherein sizes of the first plurality of transistors form a geometric sequence having a scale factor k, and are equal to W/L, kW/L, k 2 W/L, k 3 W/L, . . . , k N-1 W/L, where N represents the first number.

8 . The electronic device of claim 7 , wherein k is equal to 2, and a subset of the first plurality of transistors are selected based on a binary scheme, such that a total size of the selected subset of the first plurality of transistors matches the bias current and the data rate.

9 . The electronic device of claim 4 , wherein the subset of the two differential transistor groups includes a first subset of the first plurality of transistors and a second subset of the second plurality of transistors that are identical to the first subset of the first plurality of transistors.

10 . The electronic device of claim 1 , further comprising:
a plurality of biasing circuits coupled to the two differential transistor groups, wherein each biasing circuit is coupled to a respective one of the first plurality of transistors and the second plurality of transistors, and each biasing circuit further includes:
a DC path coupled to a DC bias voltage source for the respective transistor; and
an input path coupled to a respective one of the first and second input signals.

11 . The electronic device of claim 10 , wherein:
each transistor of the two differential transistor groups is configured to be (1) selected when a DC bias voltage source of a respective biasing circuit is electrically coupled to a first predefined biasing voltage level, and (2) deselected when the DC bias voltage source of the respective biasing circuit is electrically coupled to a second predefined biasing voltage level; for each transistor of the subset of the two differential transistor groups, the DC bias voltage source of the respective biasing circuit is electrically coupled to the first predefined biasing voltage level; and for each remaining transistor of two differential transistor groups, the DC bias voltage source of the respective biasing circuit is electrically coupled to the second predefined biasing voltage level.

12 . The electronic device of claim 11 , wherein each transistor is an N-type MOSFET, and the first predefined biasing voltage level is higher than the second predefined biasing voltage, and the second predefined biasing voltage is configured to turn off the respective transistor.

13 . The electronic device of claim 11 , wherein each transistor is a P-type MOSFET, and the first predefined biasing voltage level is lower than the second predefined biasing voltage, and the second predefined biasing voltage is configured to turn off the respective transistor.

14 . The electronic device of claim 10 , wherein the DC path includes a resistor coupled between the DC bias voltage source and a gate of the respective transistor, and the input path includes at least a capacitor coupled between a respective input and the gate of the respective transistor, the respective input configured to receive the respective one of the first and second input signals.

15 . The electronic device of claim 1 , wherein the first plurality of transistors are configured to output a first output signal and the second plurality of transistors are configured to output a second output signal, and the first and second output signals form the pair of differential output signals.

16 . The electronic device of claim 1 , wherein the electronic device is a receiver device having a continuous time linear equalizer (CTLE) applied in a serializer/deserializer application.

17 . The electronic device of claim 3 , wherein the control signal is configured to enable a subset of the current source, the subset of the two differential transistor groups, or both, such that the pair of differential output signals are generated from the pair of differential input signals based on the data rate of the data carried by the pair of differential input signals.

18 . A method, comprising:
based on a data rate of data carried by a pair of differential input signals:
generating a bias current;
receiving a multibit control signal that is distinct from the pair of differential input signals; and
selecting, based on the control signal, a subs

Assignees

• Parade Tech Ltd

Inventors

• She Min
• Lee Kochung

Classifications

• H04B1/123 Primary

  using adaptive balancing or compensation means (adaptive filter circuits and algorithms H03H) · CPC title

• H03K19/018514

  with at least one differential stage (H03K19/018528 and H03K19/018542 take precedence) · CPC title

• H03K17/122

  in field-effect transistor switches · CPC title

• H03K17/6874 Primary

  in a symmetrical configuration · CPC title