Multimode equalization circuitry

Patent metadata

Field	Value
Publication number	US-9537681-B1
Application number	US-201414536417-A
Country	US
Kind code	B1
Filing date	Nov 7, 2014
Priority date	Mar 31, 2014
Publication date	Jan 3, 2017
Grant date	Jan 3, 2017

Abstract

An integrated circuit may include receiver circuitry that receives data from an external device. Such receiver circuitry may include, among other things, equalization circuitry that may reconstruct the received data before transmitting the received data to other parts of the integrated circuit. The receiver circuitry may include two different equalization circuits. A first equalization circuit may perform equalization on the received data to generate a first equalized output while a second equalization circuit may generate a second equalized output. The receiver circuitry may further include an amplifier circuit that selectively amplifies either the first or second equalized output from the respective first and second equalization circuits based on the data rate of the received data.

First claim

What is claimed is:

1. Receiver circuitry that receives data from an external device, comprising:
a first equalization circuit that performs equalization on the received data and that generates a corresponding first equalized output, wherein the first equalization circuit comprises a plurality of equalizer circuit stages;
a second equalization circuit that performs equalization on the received data and that generates a corresponding a second equalized output, wherein the second equalization circuit is separate from the first equalization circuit, and wherein the second equalization circuit comprises a single-stage equalizer circuit; and
an amplifier circuit that outputs the first equalized output when the data has a first data rate that is less than a predetermined threshold and that outputs the second equalized output when the data has a second data rate that is greater than the predetermined threshold.

2. The receiver circuitry defined in claim 1 , wherein the first and second equalization circuits are continuous time linear equalization (CTLE) circuits.

3. The receiver circuitry defined in claim 1 , wherein the amplifier circuit comprises a variable gain amplifying circuit.

4. The receiver circuitry defined in claim 3 , wherein the variable gain amplifying circuit comprises:
a biasing circuit that adjusts a voltage that is supplied to the variable gain amplifying circuit.

5. The receiver circuitry defined in claim 1 , wherein the amplifier circuit includes an operational amplifier coupled in a negative feedback loop.

6. The receiver circuitry defined in claim 1 , wherein the second data rate is at least two times the first data rate.

7. An integrated circuit that receives a data stream, comprising:
equalization circuitry that equalizes the data stream,
the equalization circuitry comprising a multi-stage equalization circuit that equalizes the data stream to produce a first equalized output and further comprising a single-stage equalization circuit that equalizes the data stream to produce a second equalized output, wherein the multi-stage equalization circuit and the single-stage equalization circuit are separate circuits, wherein the multi-stage equalization circuit is a continuous time linear equalization (CTLE) circuit, and wherein the single-stage equalization circuit is another CTLE circuit; and
amplifying circuitry that receives the first and second equalized outputs from the equalization circuitry and that amplifies a selected one of the first and second equalized outputs.

8. The integrated circuit defined in claim 7 , wherein the amplifying circuitry comprises adjustable gain amplifying circuitry.

9. The integrated circuit defined in claim 7 , wherein the multi-stage and single-stage equalization circuits comprise differential circuits.

10. The integrated circuit defined in claim 7 , wherein the amplifying circuitry selectively amplifies the selected one of the first and second equalized outputs based on the data rate of the data stream.

11. A method of operating an integrated circuit comprising:
receiving data from an off-chip device;
determining a data rate of the received data;
using a first equalization path that includes a multi-stage equalization circuit to equalize the received data exhibiting a first data rate;
using a second equalization path that includes a single-stage equalization circuit to equalize the received data exhibiting a second data rate, wherein the second data rate is greater than the first data rate, and wherein the second equalization path is separate from the first equalization path; and
using multiplexing circuitry to output an equalized output by selectively routing the equalized data from one of the first and second equalization paths.

12. The method defined in claim 11 , further comprising:
with amplifier circuitry, amplifying the equalized output from the first equalization path when the first data rate is less than a threshold and amplifying the equalized output from the second equalization path when the second data rate is greater than the threshold.

13. The method defined in claim 12 , further comprising:
when the data rate of the received data is the first data rate, performing a continuous time linear equalization (CTLE) operation using the multi-stage equalization circuit; and
when the data rate of the received data is the second data rate that is greater than the first data rate, performing the CTLE operation using the single-stage equalization circuit.

14. The method defined in claim 12 , wherein the amplifier circuitry exhibits a gain, the method further comprising:
with a biasing circuit in the amplifier circuitry, adjusting a voltage that is supplied to the amplifier circuitry to control the gain of the amplifier circuitry.

15. The method defined in claim 11 , wherein the multiplexing circuitry selectively enables one of the first and second equalization paths based on a plurality of configuration random access memory (CRAM) bits.

16. The method defined in claim 12 further comprising:
with an operational amplifier, providing a negative feedback signal to the amplifier circuitry.

Assignees

• Altera Corp

Inventors

• Chan Allen K
• Giridharan Vishal

Classifications

• H04L25/03878

  Line equalisers; line build-out devices · CPC title

• H04L25/03057 Primary

  with a recursive structure (H04L25/03031 takes precedence) · CPC title

• H04L25/03885

  adaptive · CPC title

• H04L2025/03439

  Fixed structures · CPC title

• H04L25/03012 Primary

  operating in the time domain (H04L25/03165, H04L25/03178 take precedence) · CPC title