Universal serial bus (USB) host data switch with integrated equalizer

Patent metadata

Field	Value
Publication number	US-11689201-B2
Application number	US-202117385699-A
Country	US
Kind code	B2
Filing date	Jul 26, 2021
Priority date	Jul 26, 2021
Publication date	Jun 27, 2023
Grant date	Jun 27, 2023

Abstract

An aspect relates to an apparatus including a first pair of switching devices configured to selectively couple an application processor to a Universal Serial Bus (USB) differential data transmission lines; a USB host port connector coupled to the USB differential data transmission lines; a second pair of switching devices configured to selectively couple an audio circuit to the USB differential data transmission lines; and an equalizer including differential terminals coupled to the USB differential data transmission lines, respectively.

First claim

What is claimed:

1 . An apparatus, comprising:
a first pair of switching devices configured to selectively couple an application processor to Universal Serial Bus (USB) differential data transmission lines; a second pair of switching devices configured to selectively couple an audio circuit to the USB differential data transmission lines; and an equalizer including differential terminals coupled to the USB differential data transmission lines, respectively, wherein the equalizer comprises:
a first current source;
a first field effect transistor (FET) coupled in series with the first current source between a first voltage rail and a negative one of the USB differential data transmission lines, wherein the first FET includes a first gate coupled to a positive one of the USB differential data transmission lines;
a second current source;
a second FET coupled in series with the second current source between the first voltage rail and the positive one of the USB differential data transmission lines, wherein the second FET includes a second gate coupled to the negative one of the USB differential data transmission lines; and
a capacitor coupled between a first node between the first current source and the first FET, and a second node between the second current source and the second FET.

2 . The apparatus of claim 1 , wherein the capacitor comprises a variable capacitor.

3 . The apparatus of claim 1 , wherein the equalizer further comprises a resistor coupled between the first and second nodes.

4 . The apparatus of claim 3 , wherein the resistor comprises a variable resistor.

5 . The apparatus of claim 1 , wherein the first and second current sources comprise first and second variable current sources, respectively.

6 . The apparatus of claim 1 , wherein the first and second FETs comprise p-channel metal oxide semiconductor (PMOS) FETs, respectively.

7 . An apparatus, comprising:
a first pair of switching devices configured to selectively couple an application processor to Universal Serial Bus (USB) differential data transmission lines; a second pair of switching devices configured to selectively couple an audio circuit to the USB differential data transmission lines; and an equalizer including differential terminals coupled to the USB differential data transmission lines, respectively, wherein the equalizer comprises:
a first resistor;
a first field effect transistor (FET);
a first current source coupled in series with the first resistor and the first FET between a first voltage rail and a second voltage rail;
a second resistor;
a second FET coupled in series with the second resistor and the first current source between the first and second voltage rails;
a first capacitor coupled between a first node between the first resistor and the first FET, and a positive one of the USB differential data transmission lines; and
a second capacitor coupled between a second node between the second resistor and the second FET, and a negative one of the USB differential data transmission lines.

8 . The apparatus of claim 7 , wherein the equalizer further comprises:
a third capacitor coupled between the negative one of the USB differential data transmission lines and a first gate of the first FET; and a fourth capacitor coupled between the positive one of the USB differential data transmission lines and a second gate of the second FET.

9 . The apparatus of claim 7 , wherein the equalizer further comprises:
a gate bias voltage source; a third resistor coupled between the gate bias voltage source and a first gate of the first FET; and a fourth resistor coupled between the gate bias voltage source and a second gate of the second FET.

10 . The apparatus of claim 7 , wherein the first and second capacitors comprise first and second variable capacitors, respectively.

11 . The apparatus of claim 7 , wherein the first current source comprises a variable current source.

12 . The apparatus of claim 7 , wherein the first and second FETs comprise n-channel metal oxide semiconductor (NMOS) FETs, respectively.

13 . The apparatus of claim 7 , wherein the equalizer further comprises:
a second current source; a third FET coupled in series with the second current source between the first or a third voltage rail and the first node, wherein the third FET includes a third gate coupled to the second node; a third current source; a fourth FET coupled in series with the third current source between the first or the third voltage rail and the second node, wherein the fourth FET includes a fourth gate coupled to the first node; and a third capacitor coupled between a third node between the second current source and the third FET, and a fourth node between the third current source and the fourth FET.

14 . The apparatus of claim 13 , wherein the third capacitor comprises a variable capacitor.

15 . The apparatus of claim 13 , wherein the second and third current sources comprise variable current sources, respectively.

16 . The apparatus of claim 1 , wherein the first pair of switching devices are coupled between differential data outputs of the application processor and the USB differential data transmission lines, respectively.

17 . The apparatus of claim 1 , wherein the audio circuit comprises stereo amplifiers.

18 . The apparatus of claim 1 , further comprising:
a battery charger circuit including data ports; and a third pair of switching devices coupled between the data ports of the battery charger circuit and the USB differential data transmission lines, respectively.

19 . The apparatus of claim 1 , further comprising an overvoltage protection (OVP) circuit coupled to the USB differential data transmission lines.

20 . A wireless communication device, comprising:
at least one antenna; a transceiver coupled to the at least one antenna; one or more signal processing cores coupled to the transceiver; a Universal Serial Bus (USB) data switch coupled to the one or more signal processing cores, wherein the USB data switch comprises:
a first pair of switching devices configured to selectively couple an application processor to USB differential data transmission lines;
a second pair of switching devices configured to selectively couple an audio circuit to the USB differential data transmission lines; and
an equalizer including differential terminals coupled to the USB differential data transmission lines, respectively, wherein the equalizer comprises:
a first current source;
a first field effect transistor (FET) coupled in series with the first current source between a first voltage rail and a negative one of the USB differential data transmission lines, wherein the first FET includes a first gate coupled to a positive one of the USB differential data transmission lines;
a second current source;
a second FET coupled in series with the second current source between the first voltage rail and the positive one of the USB differential data transmission lines, wherein the second FET includes a second gate coupled to the negative one of the USB differential data transmission lines; and
a capacitor coupled between a first node between the first current source and the first FET, and a second node between the second current source and the second FET.

21 . The wireless communication device of claim 20 , further comprising a third pair of switching devices configured to selectively couple a battery charger circuit to the USB differential data transmission li

Assignees

• Qualcomm Inc

Inventors

• Dhanasekaran Vijayakumar
• Abdelfattah Aly Khaled Mahmoud

Classifications

• H02J7/40

  characterised by the exchange of charge or discharge related data · CPC title

• G06F2213/0042

  Universal serial bus [USB] · CPC title

• H03K17/6874 Primary

  in a symmetrical configuration · CPC title

• H02J7/00032

  Electricity · mapped topic

• G06F13/4282

  on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247) · CPC title