Device, method and system to mitigate stress on hybrid bonds in a multi-tier arrangement of chiplets

Patent metadata

Field	Value
Publication number	US-12456702-B2
Application number	US-202117359380-A
Country	US
Kind code	B2
Filing date	Jun 25, 2021
Priority date	Jun 25, 2021
Publication date	Oct 28, 2025
Grant date	Oct 28, 2025

Abstract

Techniques and mechanisms for mitigating stress on hybrid bonded interfaces in a multi-tier arrangement of integrated circuit (IC) dies. In an embodiment, first dies are bonded at a host die each via a respective one of first hybrid bond interfaces, wherein a second one or more dies are coupled to the host die each via a respective one of the first dies, and via a respective second hybrid bond interface. Stress at one of the hybrid bond interfaces is mitigated by properties of a first dielectric layer that extends to that hybrid bond interface. In another embodiment, stress at a given one of the hybrid bond interfaces is mitigated by properties of a dummy chip—or alternatively, properties of a patterned encapsulation structure—which is formed on the given hybrid bond interface.

First claim

What is claimed is:

1. A packaged device comprising:
a host die;
a first plurality of dies each bonded at the host die via a respective hybrid bond interface of a first plurality of hybrid bond interfaces;
a second one or more dies each coupled to the host die via a respective one of the first plurality of dies, and via a respective hybrid bond interface of a second one or more hybrid bond interfaces, wherein a first tier of a multi-tier configuration of multiple dies comprises the first plurality of dies, and wherein a second tier of the multi-tier configuration comprises the second one or more dies;
an encapsulation structure comprising a first body of a first mold compound material, and a second body of a second mold compound material;

wherein:
the first mold compound material and the second mold compound material have different compositions;
the first body and the second body each extend in a region between a first die and a second die of the multiple dies;
the first tier comprises the first die and the second die; and
the first body and the second body each extend to both:
a first vertical level of the first plurality of hybrid bond interfaces; and
a second vertical level of the second one or more hybrid bond interfaces.

2. The packaged device of claim 1 , wherein, in the region, the first body adjoins each of two opposite sides of the second body.

3. The packaged device of claim 1 , wherein a contiguous portion of the encapsulation structure extends across the region to each of the first die and the second die.

4. The packaged device of claim 3 , wherein each of the first body and the second spans at least a respective 10% of a total horizontal distance in the region between the first die and the second die.

5. The packaged device of claim 1 , wherein the one of the first tier or the second tier further comprises a third die coupled to the host die via a respective hybrid bond interface;
wherein the encapsulation structure further comprises a third body of the second mold compound material;
wherein the first body further extends into a second region between the second die and the third die; and
wherein the third body extends into the second region.

6. The packaged device of claim 1 , wherein the other of the first tier or the second tier comprises a third die and a fourth die each coupled to the host die via a respective hybrid bond interface;
wherein the encapsulation structure further comprises a third body of the second mold compound material;
wherein the first body further extends into a second region between the third die and the fourth die; and
wherein the third body extends into the second region.

7. The packaged device of claim 1 , wherein a coefficient of thermal expansion (CTE) of the second mold compound material is less than 5 parts per million per degree Kelvin (ppm/° K).

8. The packaged device of claim 1 , wherein a Young's modulus of the second mold compound material is less than 100 megaPascals (MPa).

9. The packaged device of claim 1 , wherein:
the region is a first region;
the encapsulation structure further comprises a third body of the second mold compound material;
the first body and the third body each extend in a second region between a third die and a fourth die of the multiple dies;
the second tier comprises the third die and the fourth die;
the first body and the third body each extend to the second vertical level; and
the first body and the third body each span a vertical height of the second tier.

Assignees

• Intel Corp

Inventors

• Jun Kimin
• Eid Feras
• Elsherbini Adel
• Aleksov Aleksandar
• Liff Shawna
• Swan Johanna
• Sebot Julien

Classifications

• H10W80/00

  Direct bonding of chips, wafers or substrates · CPC title

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title

• H10W90/291

  characterised by containers, encapsulations, or other housings for the stacked chips · CPC title

• H10W90/24

  at least one of the stacked chips being laterally offset from a neighbouring stacked chip, e.g. chip stacks having a staircase shape · CPC title

• H10W90/20

  Configurations of stacked chips · CPC title