Separate peak current checkpoints for closed and open block read ICC countermeasures in NAND memory

Patent metadata

Field	Value
Publication number	US-12456531-B2
Application number	US-202318346347-A
Country	US
Kind code	B2
Filing date	Jul 3, 2023
Priority date	Apr 24, 2023
Publication date	Oct 28, 2025
Grant date	Oct 28, 2025

Abstract

To reduce spikes in the current used during read operations by a system of multiple NAND memory dies operated in parallel, relative delays between the memory dies are introduced before high current sub-operations of the read. The occurrence of the primary current peak in the read operation can depend upon the extent to which a selected memory block is programmed. For example, in a closed block the primary peak occurs when ramping up unselected word lines, while for an open block the primary read peak occurs when the bit lines are charged up. To account for these differences, determining where to introduce relative delays is based on the extent to which a block is programmed. For example, if a block fully or largely closed, delays are introduced before ramping up the unselected word lines, but otherwise adding the delays before charging up bit lines.

First claim

What is claimed is:

1. A non-volatile memory system, comprising:
a first control circuit configured to connect to a plurality of memory arrays, each of the memory arrays comprising a plurality of blocks, each block including a plurality of non-volatile memory cells, the first control circuit configured to:
select a first block of a first array on which to perform a first sensing operation, the first sensing operation including a plurality of sub-operations;
determine, based on a number of the memory cells of the first block written to a corresponding target data state, an extent to which the first block is currently programmed;
based on the determined extent to which the first block is currently programmed, determine which of the plurality of sub-operations of the first sensing operation before which to introduce an added delay and a duration of the added delay; and
issue a command to perform the first sensing operation, the command specifying the sub-operation before which the added delay is to be introduced.

2. The non-volatile memory system of claim 1 , wherein the first array has a NAND architecture in which a plurality of NAND strings are each connected to a corresponding bit line and have memory cells connected along word lines, and wherein the plurality of sub-operations include: charging unselected word lines of the first block to an unselected word line read bypass voltage; and, subsequent to charging the unselected word lines of the first block to the unselected word line read bypass voltage, charging up the corresponding bit lines.

3. The non-volatile memory system of claim 2 , wherein the first control circuit is further configured to:
in response to the first block being currently programmed to more than a first extent, introduce the delay prior to charging the unselected word lines of the first block to the unselected word line read bypass voltage; and
in response to the first block being currently programmed to less than the first extent, introduce the delay after charging the unselected word lines of the first block to the unselected word line read bypass voltage and before charging up the corresponding bit lines.

4. The non-volatile memory system of claim 1 , wherein the first control circuit comprises a non-volatile memory controller and the non-volatile memory system further comprises:
a plurality of memory dies and each of the memory arrays is part of a corresponding memory die, wherein the non-volatile memory controller operates the plurality of memory dies in parallel, the non-volatile memory controller further configured:
for each of the memory dies, select a block, including the selected first block of the first array, on which to perform the first sensing operation;
for each of the selected blocks, determine a corresponding extent to which the selected block is currently programmed;
based on the determined corresponding extent to which each of the selected blocks is currently programmed, determine for each of the memory dies the sub-operation of the first sensing operation before which to introduce a delay and a corresponding amount of the delay, where each memory dies has a different corresponding amount of the delay; and
issue commands to the plurality of memory dies to perform the first sensing operation, the commands specifying for each of the memory dies the sub-operation before which the delay is to be introduced and the corresponding amount of the delay.

5. The non-volatile memory system of claim 4 , wherein each of the memory dies further comprises one or more control circuits configured to execute the issued commands with the introduced delays on the dies concurrently.

6. The non-volatile memory system of claim 4 , further comprising:
a corresponding control die for each of the memory dies, each control die separate from and bonded to the corresponding memory die and comprising one or more control circuits configured to execute the issued commands with the introduced delays on the dies concurrently.

7. The non-volatile memory system of claim 1 , wherein the first block of the first array comprises a plurality of word lines and the extent to which the first block is currently programmed is based on a number of the word lines of the first block that have been previously written.

8. The non-volatile memory system of claim 7 , where, to determine the extent to which the first block is currently programmed the first control circuit is configured to:
determine whether a number of word lines that have been previously written exceed a limit.

9. The non-volatile memory system of claim 1 , wherein the first sensing operation is a read operation.

10. The non-volatile memory system of claim 1 , wherein the first sensing operation is a verify operation.

11. The non-volatile memory system of claim 1 , wherein the first control circuit is further configured to:
maintain for each of the blocks an indication of the extent to which the first block has previously been programmed.

12. A method, comprising:
selecting a block of non-volatile memory cells on each of a plurality of memory dies;
for each of the selected blocks, determining, based on a number of the memory cells of the first block written to a corresponding target data state, whether the block has been written to more than a first extent; and
concurrently performing a sensing operation on the selected blocks, where the sensing operation comprises a plurality of sub-operations and concurrently performing the sensing operation comprises:
for blocks programmed more than the first extent, introduce an additional amount of delay before a first of the sub-operations, each of the blocks programmed more than the first extent having a different amount of introduced delay; and
for blocks not programmed more than the first extent, introduce an additional amount of delay before a second of the sub-operations, each of the blocks not programmed more than the first extent having a different amount of introduced delay.

13. The method of claim 12 , wherein each of the blocks of non-volatile memory cells comprises a plurality of NAND strings each connected to a corresponding bit line and having memory cells connected along corresponding word lines, wherein the first sub-operation includes charging unselected word lines of the block to a read bypass voltage, and wherein the second sub-operation includes charging the block's corresponding bit lines.

14. The method of claim 12 , wherein each of the selected blocks comprises a plurality of word lines and the extent to which the block is currently programmed is based on a number of the word lines that have been previously programmed.

15. The method of claim 12 , further comprising:
maintaining for each of the blocks an indication of the extent to which the first block has previously been programmed.

16. The method of claim 12 , wherein the sensing operation is a read operation.

17. A non-volatile memory system, comprising:
a plurality of memory dies each having a plurality of blocks of non-volatile memory cells; and
one or more control circuits connected to the plurality of memory dies, the one or more control circuits configured to:
maintain, for each of the blocks, an indication of whether the block is open or closed based on a number of the memory cells of the first block written to a corresponding target data state;
select a block from each of a plurality of the memory dies; and
concurrently perform a sensing operation on the selected blocks, the sensing operation comprising a plurality sub-operations, where, to concurrently perform the sens

Assignees

• Sandisk Technologies Inc

Inventors

• Zainuddin Abu Naser
• Shlick Mark
• Yuan Jiahui

Classifications

• G11C16/32

  Timing circuits · CPC title

• G11C16/102

  External programming circuits, e.g. EPROM programmers; In-circuit programming or reprogramming; EPROM emulators · CPC title

• G11C16/0433

  comprising cells containing a single floating gate transistor and one or more separate select transistors · CPC title

• G11C11/5642

  Sensing or reading circuits; Data output circuits · CPC title

• G11C11/5628

  Programming or writing circuits; Data input circuits · CPC title