Ad hoc digital multi-die polling for peak icc management

Patent metadata

Field	Value
Publication number	US-2016293264-A1
Application number	US-201514928992-A
Country	US
Kind code	A1
Filing date	Oct 30, 2015
Priority date	Apr 3, 2015
Publication date	Oct 6, 2016
Grant date	—

Abstract

Systems and methods for reducing peak power supply current in a non-volatile memory system that includes a plurality of memory die are described. In some cases, prior to a first memory die of the plurality of memory die performing a particular memory operation (e.g., a programming operation), the first memory die may poll other memory die of the plurality of memory die to determine a total peak power supply current for the plurality of memory die. In response to detecting that the total peak power supply current for the plurality of memory die is at or above a peak current threshold (e.g., more than 200 mA), the first memory die may delay the performance of the particular memory operation or slow down the performance of the particular memory operation.

First claim

What is claimed is:

1 . An apparatus, comprising:
a first memory die; and a second memory die configured to acquire a power supply current value for the first memory die and set a rate for charging up an internal node of the second memory die based on the power supply current value, the second memory die configured to charge up the internal node at the rate.

2 . The apparatus of claim 1 , wherein:
the second memory die configured to charge up the internal node from a first voltage to a second voltage greater than the first voltage at the rate, the second memory die configured to acquire a second power supply current value for the first memory die subsequent to charging up the internal node at the rate, the second memory die configured to adjust the rate for charging up the internal node based on the second power supply current value, the second memory die configured to charge up the internal node from the second voltage to a third voltage greater than the second voltage at the adjusted rate.

3 . The apparatus of claim 2 , wherein:
the second memory die configured to increase the rate for charging up the internal node based on the second power supply current value.

4 . The apparatus of claim 1 , wherein:
the second memory die configured to identify a memory operation scheduled for the second memory die and acquire the power supply current value for the first memory die from the first memory die in response to identifying the scheduled memory operation.

5 . The apparatus of claim 1 , wherein:
the power supply current value for the first memory die is equal to a peak power supply current value for the first memory die.

6 . The apparatus of claim 1 , wherein:
the internal node comprises a bit line.

7 . The apparatus of claim 1 , wherein:
the first memory die comprises a first non-volatile memory die; and the second memory die comprises a second non-volatile memory die.

8 . The apparatus of claim 1 , wherein:
the second memory die includes non-volatile memory that is monolithically formed in one or more physical levels of memory cells having active areas disposed above a silicon substrate.

9 . A method, comprising:
identifying a memory operation to be performed using a memory die of a plurality of memory die, the memory operation includes charging up an internal node of the memory die; determining a first total power supply current for the plurality of memory die prior to performing the memory operation; setting a ramp rate for charging up the internal node based on the first total power supply current; and charging up the internal node from a first voltage to a second voltage greater than the first voltage at the ramp rate.

10 . The method of claim 9 , further comprising:
determining a second total power supply current for the plurality of memory die subsequent to setting the ramp rate; adjusting the ramp rate for charging up the internal node based on the second total power supply current; and charging up the internal node from the second voltage to a third voltage greater than the second voltage at the adjusted ramp rate.

11 . The method of claim 10 , wherein:
the adjusting the ramp rate comprises increasing the ramp rate.

12 . The method of claim 9 , wherein:
the first total power supply current for the plurality of memory die comprises a sum of power supply current values for each memory die of the plurality of memory die.

13 . The method of claim 9 , wherein:
the memory operation comprises a programming operation; and the internal node comprises an output of a charge pump configured to generate a programming voltage during the programming operation.

14 . The method of claim 9 , wherein:
the determining a first total power supply current for the plurality of memory die includes receiving from a set of memory die of the plurality of memory die power supply current information associated with the amount of power supply current being consumed by the set of memory die.

15 . The method of claim 9 , wherein:
the internal node comprises a bit line.

16 . The method of claim 9 , wherein:
the plurality of memory die comprises eight NAND Flash memory die.

17 . The method of claim 9 , wherein:
the memory die includes non-volatile memory that is monolithically formed in one or more physical levels of memory cells having active areas disposed above a silicon substrate.

18 . A system, comprising:
a first memory die; and a second memory die including a polling circuit configured to determine a power supply current consumed by the first memory die and determine a difference between the power supply current consumed by the first memory die and a maximum current threshold, the polling circuit configured to set a precharge time for charging up an internal node of the second memory die based on the difference, the second memory die configured to charge up the internal node based on the precharge time.

19 . The system of claim 18 , wherein:
the polling circuit configured to determine a second power supply current consumed by the first memory die and determine a second difference between the second power supply current consumed by the first memory die and the maximum current threshold, the second memory die configured to adjust the precharge time for charging up the internal node based on the second difference.

20 . The system of claim 19 , wherein:
the internal node comprises a bit line; and the second memory die configured to increase the precharge time for charging up the bit line based on the second difference.

Assignees

• Sandisk Technologies Inc

Inventors

• Al-Shamma Ali
• Moogat Farookh
• Siau Chang
• Shah Grishma
• Louie Kenneth
• Nguyen Khanh
• Verma Kapil

Classifications

• G11C16/24

  Bit-line control circuits · CPC title

• G11C16/30 Primary

  Power supply circuits · CPC title

• G11C5/02

  Disposition of storage elements, e.g. in the form of a matrix array · CPC title

• G11C5/14

  Power supply arrangements {, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels} · CPC title

• G11C5/141

  Battery and back-up supplies · CPC title