Memory device including address table and operating method for memory controller

Patent metadata

Field	Value
Publication number	US-12455829-B2
Application number	US-202318140974-A
Country	US
Kind code	B2
Filing date	Apr 28, 2023
Priority date	May 2, 2022
Publication date	Oct 28, 2025
Grant date	Oct 28, 2025

Abstract

A memory device includes; a memory cell array, and a command/address decoder including a buffer memory, a first decoding logic circuit configured to decrypt command/address information, and a second decoding logic circuit configured to decrypt an address table. The command/address decoder is configured to decrypt a first command received from a memory controller through the first decoding logic circuit to obtain a table synchronization command, decrypt data received from the memory controller after a predefined latency from receipt of the first command through the second decoding logic circuit to obtain an address table, store the address table in the buffer memory, decrypt a second command received from the memory controller through the first decoding logic circuit to obtain a table-based command and index information associated with the address table, and execute the table-based command with respect to an address corresponding to the index information.

First claim

What is claimed is:

1. A memory device comprising:
a memory cell array; and
a command/address decoder including a buffer memory, a first decoding logic circuit configured to decrypt command/address information, and a second decoding logic circuit configured to decrypt an address table,
wherein the command/address decoder is configured to
decrypt a first command received from a memory controller through the first decoding logic circuit to obtain a table synchronization command,
decrypt data received from the memory controller, after a predefined latency from receipt of the first command, through the second decoding logic circuit to obtain the address table, the address table being configured to store an index mapped with address information of the memory device,
store the address table in the buffer memory,
decrypt a second command received from the memory controller through the first decoding logic circuit to obtain a table-based command and index information associated with the index of the address table, and
execute the table-based command with respect to an address corresponding to the index based on the index information.

2. The memory device of claim 1 , wherein the first command and the second command are communicated to the memory device through a command/address pin, and
the data received after the predefined latency from the receipt of the first command is communicated to the memory device through a data pin.

3. The memory device of claim 2 , wherein the data received from the memory controller after the predefined latency from receipt of the first command is generated by the memory controller by encoding an address table to be stored in the buffer memory.

4. The memory device of claim 2 , further comprising:
a multiplexer/demultiplexer configured to receive data from the first decoding logic circuit and further configured to exchange data with the buffer memory and the data pin.

5. The memory device of claim 1 , wherein the address table is a sub-table particularly associated with the memory device and corresponding to a global address table referenced by the memory controller.

6. The memory device of claim 1 , wherein decrypting the first command generates a table synchronization command, and the table synchronization command includes:
a first field indicating whether the table synchronization command is a full table synchronization command or a partial table synchronization command; and
a second field indicating whether offset information is included in the table synchronization command.

7. The memory device of claim 6 , wherein the first field includes a single bit,
a logical low value for the first field indicates the full table synchronization command, and
a logical high value for the first field indicates the partial table synchronization command.

8. The memory device of claim 7 , wherein the table synchronization command further includes a third field indicating a latency from a time at which the table synchronization command is received to another time at which the data is received.

9. An operating method for a memory device, the operating method comprising:
receiving a first command from a memory controller;
decrypting the first command to obtain a table synchronization command;
decrypting data received from the memory controller after a predefined latency from receipt of the first command to obtain an address table, the address table being configured to store an index mapped with address information of the memory device;
storing the address table in a buffer memory;
receiving a second command from the memory controller;
decrypting the second command to obtain a table-based command and corresponding index information associated with the index of the address table; and
executing the table-based command with respect to an address corresponding to the index based on the index information.

10. The operating method of claim 9 , wherein the first command and the second command are communicated to the memory device from a memory controller through a command/address pin, and
the data is communicated from the memory controller to the memory device through a data pin.

11. The operating method of claim 9 , wherein the table synchronization command includes:
a first field indicating whether the table synchronization command is a full table synchronization command or a partial table synchronization command;
a second field indicating whether the table synchronization command includes offset information; and
a third field indicating a latency from a time at which the table synchronization command is received to another time at which the data is received.

12. The operating method of claim 9 , further comprising:
determining a type of the table-based command; and
obtaining at least one of a bank, a row address, and a column address corresponding to the index information and in accordance with the type of the table-based command.

13. The operating method of claim 12 , wherein the obtaining of the at least one of a bank, a row address, and a column address corresponding to the index information and in accordance with the type of the table-based command includes obtaining a bank and a row address corresponding to the index information if the table-based command is an activation command.

14. The operating method of claim 12 , wherein the obtaining of the at least one of a bank, a row address, and a column address corresponding to the index information and in accordance with the type of the table-based command includes obtaining a bank, a row address, and a column address corresponding to the index information if the table-based command is a read command or a write command.

15. The operating method of claim 12 , wherein the obtaining of the at least one of a bank, a row address, and a column address corresponding to the index information and in accordance with the type of the table-based command includes obtaining a bank corresponding to the index information if the table-based command is a precharge command.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Chinam
• Ko Taekyeong
• Kim Namhyung
• Kim Dohan
• Kim Byeongnoh
• Kim Bobae
• Lee Changmin
• Cho Kyeongjin
• CHOI Insu

Classifications

• G06F12/0284

  Multiple user address space allocation, e.g. using different base addresses (interprocessor communication G06F15/163) · CPC title

• G06F12/0292

  using tables or multilevel address translation means (G06F12/023 takes precedence; address translation in virtual memory systems G06F12/10) · CPC title

• G06F2212/1016

  Performance improvement · CPC title

• G11C8/06

  Address interface arrangements, e.g. address buffers · CPC title

• G11C8/12

  Group selection circuits, e.g. for memory block selection, chip selection, array selection · CPC title