Memory devices and memory systems with the memory devices

Patent metadata

Field	Value
Publication number	US-2021390989-A1
Application number	US-202117151496-A
Country	US
Kind code	A1
Filing date	Jan 18, 2021
Priority date	Jun 15, 2020
Publication date	Dec 16, 2021
Grant date	—

Abstract

A memory device includes a memory area configured to store data, a data input/output (I/O) part configured to receive and output data through an external bus, an I/O buffering part coupled between the memory area and the data I/O part to store data outputted from the memory area, and a first internal data transmission line providing a data transmission path between the memory area and the I/O buffering part and having a first bandwidth which is greater than a bandwidth of the external bus. Data transmission between the memory area and the I/O buffering part through the first internal data transmission line is executed using a portion of the first bandwidth in a first operation mode and is executed using all of the first bandwidth in a second operation mode.

First claim

What is claimed is:

1 . A memory device comprising:
a memory area configured to store data; a data input/output (I/O) part configured to receive and output data through an external bus; an I/O buffering part coupled between the memory area and the data I/O part, the I/O buffering part configured to store data outputted from the memory area; and a first internal data transmission line providing a data transmission path between the memory area and the I/O buffering part and having a first bandwidth which is greater than a bandwidth of the external bus, wherein data transmission between the memory area and the I/O buffering part through the first internal data transmission line is executed using a portion of the first bandwidth in a first operation mode and is executed using all of the first bandwidth in a second operation mode.

2 . The memory device of claim 1 ,
wherein the memory area includes a plurality of matrices; wherein each of the plurality of matrices includes a memory cell array having a plurality of memory cells respectively disposed at cross points of a plurality of rows and a plurality of columns and a sense/amplification circuit having input lines and output lines; and wherein the sense/amplification circuit is configured to receive data of all columns in a selected row designated by a row address among the plurality of rows in response to an active command in the first operation mode and the second operation mode, is configured to output data of a selected column designated by a column address among the plurality of columns in response to a read command in the first operation mode, and is configured to output data of all columns in the selected row in response to the read command in the second operation mode.

3 . The memory device of claim 2 , further comprising:
a row decoder configured to receive the active command and the row address to activate the selected row designated by the row address; and a column decoder configured to receive the read command and the column address to activate the selected column designated by the column address in the first operation mode and configured to receive the read command to activate all columns in the selected row in the second operation mode.

4 . The memory device of claim 1 ,
wherein the memory area is configured to output data of a selected column designated by a column address among data of all columns in a selected row designated by a row address through the first internal data transmission line in the first operation mode; and wherein the memory area is configured to output the data of all columns in the selected row designated by the row address through the first internal data transmission line in the second operation mode.

5 . The memory device of claim 4 ,
wherein the memory area includes “K” matrices (where, “K” is a natural number equal to or greater than two); wherein each of the “K” matrices has “M” rows and “N” columns intersecting the “M” rows (where, “M” is a natural number equal to or greater than two, and “N” is a natural number equal to or greater than two); wherein the first bandwidth of the first internal data transmission line is “K×N” bits; wherein only “K” bits of the first internal data transmission line are used in the first operation mode, and all of the “K×N” bits of the first internal data transmission line are used in the second operation mode.

6 . The memory device of claim 1 ,
wherein the memory area includes “K” matrices (where, “K” is a natural number equal to or greater than two); wherein each of the matrices has “M” rows and “N” columns intersecting the “M” rows (where, “M” is a natural number equal to or greater than two, and “N” is a natural number equal to or greater than two); and wherein the I/O buffering part includes: a plurality of buffer memories configured to store data outputted from the plurality of matrices, respectively; and a selection/output part configured to receive data outputted from the plurality of buffer memories and to sequentially output the data which are outputted from the plurality of buffer memories.

7 . The memory device of claim 6 ,
wherein each of the plurality of buffer memories is configured to receive and store 1-bit data outputted from one of the plurality of matrices in the first operation mode and is configured to receive and store “N”-bit data outputted from one of the plurality of matrices in the second operation mode; wherein the plurality of buffer memories are configured to output “K”-bit data in the first operation mode and are configured to output “K×N”-bit data in the second operation mode.

8 . The memory device of claim 7 , wherein the plurality of buffer memories are configured to receive data in parallel and to output the data in parallel.

9 . The memory device of claim 7 ,
wherein the selection/output part includes a plurality of input terminals corresponding to respective buffer memories of the plurality of buffer memories; and wherein each of the plurality of input terminals includes “N”-number of sub-input terminals corresponding to respective columns of the “N” columns.

10 . The memory device of claim 9 ,
wherein the selection/output part is configured to receive a first mode selection control signal in the first operation mode and to receive a second mode selection control signal and a column address in the second operation mode; wherein the selection/output part is configured to sequentially output a plurality of 1-bit data, which are inputted to the plurality of input terminals, in response to the first mode selection control signal; and wherein the selection/output part is configured to output data, which is inputted to a sub-input terminal corresponding to a selected column designated by the column address among the “N” sub-input terminals included in each of the plurality of input terminals, in response to the second mode selection control signal.

11 . The memory device of claim 1 , wherein the bandwidth of the external bus is the same as the number of bits of the first internal data transmission line used in the first operation mode.

12 . A memory system comprising:
a memory device including a memory area configured to store data and an input/output (I/O) buffering part configured to store data outputted from the memory area; and a memory controller configured to control read operations of the memory device, wherein the memory device is configured to store data of all columns in a selected row designated by a row address among a plurality of rows in the memory area into the I/O buffering part in response to an external command outputted from the memory controller and is configured to output data of a selected column designated by a column address among the data stored in the I/O buffering part, and wherein the memory controller is configured to perform a scheduling operation for successively executing read request commands having the same row address among a plurality of read request commands for performing read operations of the memory device.

13 . The memory system of claim 12 , wherein the memory controller includes:
a read queue configured to store the plurality of read request commands; and a scheduler configured to control an output sequence of the plurality of read request commands stored in the read queue.

14 . The memory system of claim 13 , wherein the scheduler is configured to maintain, when a first row address of a first read request command on standby for a first output or in current execution among a plurality of read request commands stored in the read queue is the same as a second row address of a s

Assignees

• Sk Hynix Inc

Inventors

• Song Choung Ki

Classifications

• G11C7/1084 Primary

  Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load · CPC title

• G11C11/4093

  Input/output [I/O] data interface arrangements, e.g. data buffers · CPC title

• G11C11/4087

  Address decoders, e.g. bit - or word line decoders; Multiple line decoders · CPC title

• G11C7/1057

  Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load · CPC title

• G11C11/4096 Primary

  Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches · CPC title