Integrated circuit devices and methods of manufacturing the same

Patent metadata

Field	Value
Publication number	US-12453175-B2
Application number	US-202217851155-A
Country	US
Kind code	B2
Filing date	Jun 28, 2022
Priority date	Jun 9, 2020
Publication date	Oct 21, 2025
Grant date	Oct 21, 2025

Abstract

Integrated circuit devices may include a fin-type active region, a gate line extending on the fin-type active region, a source/drain region on the fin-type active region and adjacent to the gate line, an interlayer insulating film covering the source/drain region, a source/drain contact hole penetrating the interlayer insulating film toward the source/drain region, a metal plug in the source/drain contact hole, and a conductive barrier film covering a sidewall of the metal plug in the source/drain contact hole. The metal plug includes a lateral expansion portion and a through portion vertically extending from the lateral expansion portion toward the source/drain region. A width of the lateral expansion is greater than a width of the through portion, and a topmost surface of the conductive barrier film is closer than a topmost surface of the metal plug to the substrate.

First claim

What is claimed is:

1. An integrated circuit device comprising:
a fin-type active region extending on a substrate in a first horizontal direction;
a gate line extending on the fin-type active region in a second horizontal direction crossing the first horizontal direction;
a source/drain region on the fin-type active region and adjacent to the gate line;
an interlayer insulating film covering the source/drain region;
a source/drain contact hole penetrating the interlayer insulating film toward the source/drain region;
a metal plug in the source/drain contact hole and electrically connected to the source/drain region; and
a conductive barrier film covering a sidewall of the metal plug,
wherein the metal plug includes a lateral expansion portion in an upper portion of the source/drain contact hole and a through portion vertically extending from the lateral expansion portion toward the source/drain region,
wherein a width of the lateral expansion portion in the first horizontal direction is greater than a width of the through portion in the first horizontal direction, and
wherein a topmost surface of the conductive barrier film is closer than a topmost surface of the metal plug to the substrate.

2. The integrated circuit device of claim 1 ,
wherein a sidewall of the source/drain contact hole has a stepped shape, and the upper portion of the source/drain contact hole is wider than a lower portion of the source/drain contact hole.

3. The integrated circuit device of claim 1 ,
wherein a portion of the conductive barrier film is on a sidewall of the lateral expansion portion of the metal plug.

4. The integrated circuit device of claim 1 ,
wherein the topmost surface of the conductive barrier film is under the lateral expansion portion of the metal plug.

5. The integrated circuit device of claim 1 , further comprising:
an etch stop film on the interlayer insulating film and on the topmost surface of the metal plug; and
a capping layer between the etch stop film and the topmost surface of the metal plug.

6. The integrated circuit device of claim 1 ,
wherein the lateral expansion portion of the metal plug includes a rounded corner.

7. The integrated circuit device of claim 1 ,
wherein the lateral expansion portion of the metal plug includes a double-humped protrusion that bulges in a direction away from the substrate.

8. The integrated circuit device of claim 1 , further comprising:
a plurality of channel regions on the fin-type active region,
wherein the plurality of channel regions are spaced apart from each other in a vertical direction, are surrounded by the gate line and are in contact with the source/drain region.

9. The integrated circuit device of claim 1 , further comprising:
a contact insulating spacer covering an inner sidewall of the source/drain contact hole.

10. The integrated circuit device of claim 1 , further comprising:
a plurality of channel regions on the fin-type active region, wherein the plurality of channel regions are spaced apart from each other in a vertical direction and are in contact with the source/drain region,
wherein the gate line surrounds each of the plurality of channel regions, and
wherein the gate line includes a main gate portion extending in the second horizontal direction on the plurality of channel regions, and a plurality of sub gate portions integrally connected to the main gate portion, and at least one of the plurality of sub gate portions is between two channel regions among the plurality of channel regions.

11. The integrated circuit device of claim 10 , further comprising:
a plurality of gate insulating films, each of the plurality of gate insulating films extending between the gate line and a respective one of the plurality of channel regions,
wherein the at least one of the plurality of sub gate portions is surrounded by one of the plurality of gate insulating films.

12. An integrated circuit device comprising:
a fin-type active region extending on a substrate in a first horizontal direction;
a plurality of channel regions on the fin-type active region, the plurality of channel regions being spaced apart from each other in a vertical direction;
a gate line extending on the fin-type active region in a second horizontal direction crossing the first horizontal direction;
a gate insulating film between the gate line and the plurality of channel regions;
a source/drain region on the fin-type active region and adjacent to the gate line, the source/drain region being in contact with the plurality of channel regions;
an interlayer insulating film covering the source/drain region;
a source/drain contact hole penetrating the interlayer insulating film toward the source/drain region;
a metal plug vertically extending in the source/drain contact hole, the metal plug being electrically connected to the source/drain region and comprising a first topmost surface; and
a conductive barrier film covering a sidewall of the metal plug in the source/drain contact hole, the conductive barrier film comprising a second topmost surface closer than the first topmost surface to the substrate,
wherein the interlayer insulating film overlaps the source/drain region in the vertical direction.

13. The integrated circuit device of claim 12 ,
wherein the metal plug includes a lateral expansion portion having a first width in the first horizontal direction and a through portion vertically extending from the lateral expansion portion toward the source/drain region and having a second width smaller than the first width in the first horizontal direction.

14. The integrated circuit device of claim 12 ,
wherein a sidewall of the source/drain contact hole has a stepped shape, and an upper portion of the source/drain contact hole is wider than a lower portion of the source/drain contact hole.

15. The integrated circuit device of claim 12 ,
wherein the metal plug includes a lateral expansion portion having a first width in the first horizontal direction and a through portion vertically extending from the lateral expansion portion toward the source/drain region and having a second width smaller than the first width in the first horizontal direction, and
wherein a portion of the conductive barrier film is on a sidewall of the lateral expansion portion of the metal plug.

16. An integrated circuit device comprising:
a fin-type active region extending on a substrate in a first horizontal direction;
a plurality of channel regions on the fin-type active region, the plurality of channel regions being spaced apart from each other in a vertical direction;
a gate line extending on the fin-type active region in a second horizontal direction crossing the first horizontal direction;
a gate insulating film between the gate line and the plurality of channel regions;
a source/drain region on the fin-type active region and adjacent to the gate line, the source/drain region being in contact with the plurality of channel regions;
an interlayer insulating film covering the source/drain region;
a source/drain contact hole penetrating the interlayer insulating film toward the source/drain region;
a metal plug vertically extending in the source/drain contact hole, the metal plug being electrically connected to the source/drain region and comprising a first topmost surface; and
a conductive barrier film covering a sidewall of the metal plug in the source/drain contact hole, the conductive barrier film comprising a second topmost surface closer than the first topmost surface to the substrate,
wherein the metal plug includes a lateral expansion

Assignees

• Samsung Electronics Co Ltd

Inventors

• Bae Deokhan
• Kim Sungmin
• Park Juhun
• Lee Yuri
• Jung Yoonyoung
• Hong Sooyeon

Classifications

• H10W20/435

  Cross-sectional shapes or dispositions of interconnections · CPC title

• H10W20/40

  Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes · CPC title

• H10W20/069

  by forming self-aligned vias or self-aligned contact plugs · CPC title

• H10W20/056

  by filling conductive material into holes, grooves or trenches · CPC title

• H10W20/054

  by selectively removing parts thereof (H10W20/034 takes precedence) · CPC title