Integrated circuit devices and methods of manufacturing the same

Patent metadata

Field	Value
Publication number	US-11315926-B2
Application number	US-202117179469-A
Country	US
Kind code	B2
Filing date	Feb 19, 2021
Priority date	Jun 9, 2020
Publication date	Apr 26, 2022
Grant date	Apr 26, 2022

Abstract

Integrated circuit devices may include a fin-type active region extending on a substrate in a first horizontal direction, a gate line extending on the fin-type active region in a second horizontal direction, a source/drain region on the fin-type active region and adjacent to the gate line, and a source/drain contact pattern connected to the source/drain region. The source/drain contact pattern may include a first portion and a second portion, the first portion having a first height, and the second portion having a second height less than the first height. The source/drain contact pattern may include a metal plug in the first and second portions and a conductive barrier film on sidewalls of the metal plug in the first and second portions. A first top surface of the conductive barrier film in the second portion is lower than a top surface of the metal plug in the second portion.

First claim

What is claimed is:

1. An integrated circuit device comprising:
a fin-type active region extending on a substrate in a first horizontal direction;
a gate line extending on the fin-type active region in a second horizontal direction crossing the first horizontal direction;
a source/drain region on the fin-type active region and adjacent to the gate line; and
a source/drain contact pattern electrically connected to the source/drain region and including a first portion and a second portion, the first portion having a first height in a vertical direction, the second portion having a second height less than the first height in the vertical direction,
wherein the source/drain contact pattern includes a metal plug in the first portion and the second portion and a conductive barrier film on sidewalls of the metal plug in the first portion and the second portion, and a first top surface of the conductive barrier film in the second portion is lower than a top surface of the metal plug in the second portion relative to the substrate.

2. The integrated circuit device of claim 1 , wherein a second top surface of the conductive barrier film in the first portion and a top surface of the metal plug in the first portion are equidistant from the substrate.

3. The integrated circuit device of claim 1 , further comprising a buried insulating film on the second portion of the source/drain contact pattern and the gate line,
wherein the buried insulating film includes a buried protrusion on the second portion of the source/drain contact pattern, and the buried protrusion is in contact with the first top surface of the conductive barrier film in the second portion.

4. The integrated circuit device of claim 1 , further comprising a buried insulating film on the second portion of the source/drain contact pattern and the gate line,
wherein a top surface of the buried insulating film, a second top surface of the conductive barrier film in the first portion, and a top surface of the metal plug in the first portion are equidistant from the substrate.

5. The integrated circuit device of claim 1 , wherein the metal plug in the second portion of the source/drain contact pattern includes a protruding top portion at a higher level than the first top surface of the conductive barrier film, the protruding top portion including a flat top surface.

6. The integrated circuit device of claim 1 , wherein the metal plug in the second portion of the source/drain contact pattern includes a protruding top portion at a higher level than the first top surface of the conductive barrier film, the protruding top portion including a rounded corner.

7. The integrated circuit device of claim 1 , wherein the metal plug in the second portion of the source/drain contact pattern includes a protruding top portion at a higher level than the first top surface of the conductive barrier film, the protruding top portion including a top surface bulging in a direction away from the substrate.

8. The integrated circuit device of claim 1 , wherein the metal plug in the second portion of the source/drain contact pattern includes a protruding top portion at a higher level than the first top surface of the conductive barrier film, the protruding top portion including a double-humped protrusion bulging in a direction away from the substrate.

9. The integrated circuit device of claim 1 , further comprising:
an insulating capping line extending on the gate line in the second horizontal direction;
a buried insulating film including a main buried portion and a buried protrusion, the main buried portion being on the insulating capping line, and the buried protrusion protruding from the main buried portion toward the substrate and being in contact with the first top surface of the conductive barrier film in the second portion; and
a gate contact extending through the insulating capping line and electrically connected to the gate line,
wherein the gate contact is separated from the second portion of the source/drain contact pattern with the buried protrusion of the buried insulating film between the gate contact and the second portion of the source/drain contact pattern in the first horizontal direction.

10. The integrated circuit device of claim 1 , wherein a top surface of the first portion of the source/drain contact pattern is higher than a top surface of the gate line relative to the substrate, and the first top surface of the conductive barrier film in the second portion of the source/drain contact pattern is lower than the top surface of the gate line relative to the substrate.

11. An integrated circuit device comprising:
a plurality of fin-type active regions extending on a substrate in a first horizontal direction to be parallel to each other;
a gate line extending on the plurality of fin-type active regions in a second horizontal direction crossing the first horizontal direction;
a source/drain region on the plurality of fin-type active regions and adjacent to the gate line; and
a source/drain contact pattern electrically connected to the source/drain region,
wherein the source/drain contact pattern includes a first portion and a second portion, the first portion has a first height in a vertical direction, and the second portion has a second height less than the first height in the vertical direction,
the first portion includes a first portion of a metal plug and a first portion of a conductive barrier film on a sidewall of the first portion of the metal plug, and the second portion includes a second portion of the metal plug and a second portion of the conductive barrier film on a sidewall of the second portion of the metal plug, and
a first top surface of the first portion of the conductive barrier film and a second top surface of the first portion of the metal plug are coplanar with each other and are at a first vertical level, and a third top surface of the second portion of the conductive barrier film is lower than a fourth top surface of the second portion of the metal plug relative to the substrate.

12. The integrated circuit device of claim 11 , further comprising:
a contact insulating spacer surrounding the first portion and the second portion of the source/drain contact pattern;
an insulating capping line extending in the second horizontal direction on the gate line; and
a buried insulating film on the insulating capping line and the contact insulating spacer,
wherein the buried insulating film includes a buried protrusion that protrudes toward the substrate and is in a space defined by the third top surface of the second portion of the conductive barrier film, the sidewall of the second portion of the metal plug, and a sidewall of the contact insulating spacer.

13. The integrated circuit device of claim 11 , wherein the fourth top surface of the second portion of the metal plug is spaced apart from the third top surface of the second portion of the conductive barrier film in a vertical direction by about 1 nm to about 5 nm.

14. The integrated circuit device of claim 11 , wherein the second portion of the metal plug includes a protruding top portion at a higher level than the third top surface of the second portion of the conductive barrier film, the protruding top portion including a flat top surface.

15. The integrated circuit device of claim 11 , wherein the second portion of the metal plug includes a protruding top portion at a higher level than the third top surface of the second portion of the conductive barrier film, the protruding top portion including a rounded corner.

16. The integrated circuit device of claim 11 , wherein th

Assignees

• Samsung Electronics Co Ltd

Inventors

• Bae Deokhan
• Kim Sungmin
• Park Juhun
• Lee Yuri
• Jung Yoonyoung
• Hong Sooyeon

Classifications

• H10W20/435

  Cross-sectional shapes or dispositions of interconnections · CPC title

• H10W20/40

  Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes · CPC title

• H10W20/069

  by forming self-aligned vias or self-aligned contact plugs · CPC title

• H10W20/033

  in openings in dielectrics · CPC title

• H10W20/056

  by filling conductive material into holes, grooves or trenches · CPC title