Contact conductive feature formation and structure

Patent metadata

Field	Value
Publication number	US-10580693-B2
Application number	US-201816032416-A
Country	US
Kind code	B2
Filing date	Jul 11, 2018
Priority date	Jul 11, 2018
Publication date	Mar 3, 2020
Grant date	Mar 3, 2020

Abstract

Generally, the present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In an embodiment, a barrier layer is formed along a sidewall. A portion of the barrier layer along the sidewall is etched back by a wet etching process. After etching back the portion of the barrier layer, an underlying dielectric welding layer is exposed. A conductive material is formed along the barrier layer.

First claim

What is claimed is:

1. A method for a semiconductor process, the method comprising:
forming a dielectric welding layer along a sidewall of an opening in a dielectric layer;
forming a barrier layer on the dielectric welding layer, wherein the barrier layer includes at least one of titanium nitride, titanium oxide, tantalum nitride, and tantalum oxide;
etching back a portion of the barrier layer to expose a side surface of an upper portion of the dielectric welding layer; and
forming a conductive material on the side surface of the upper portion of the dielectric welding layer and on the barrier layer.

2. The method of claim 1 , wherein etching back the portion of the barrier layer comprises:
wet etching the barrier layer using a solution including at least one of H 2 O 2 , H 2 SO 4 , HNO 3 , NH 4 OH, or a combination thereof.

3. The method of claim 1 , wherein a portion of the conductive material is in direct contact with the side surface of the upper portion of the dielectric welding layer.

4. The method of claim 1 , wherein the dielectric welding layer includes at least one of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, and silicon oxynitride.

5. The method of claim 1 , wherein the side surface of the upper portion of the dielectric welding layer exposed by the etching back of the portion of the barrier layer is exposed to a depth from a top surface of the dielectric welding layer to a top surface of the barrier layer in a range from about 15 nm to about 25 nm.

6. The method of claim 1 , wherein a top surface of the barrier layer is lower than a top surface of the dielectric welding layer on the sidewall of the opening of the dielectric layer.

7. The method of claim 1 , wherein etching back the portion of the barrier layer comprises etching back a portion of the dielectric welding layer to expose an upper portion of the sidewall of the opening in the dielectric layer.

8. The method of claim 1 , wherein the dielectric welding layer is a silicon-containing dielectric material.

9. A structure comprising:
a dielectric layer having a sidewall, the dielectric layer being over a substrate;
a dielectric welding layer along the sidewall, the dielectric welding layer exposing an upper portion of the sidewall;
a barrier layer along the dielectric welding layer, the barrier layer exposing a side surface of an upper portion of the dielectric welding layer; and
a conductive material along the barrier layer and along the respective upper portions of the sidewall and the dielectric welding layer.

10. The structure of claim 9 , wherein the conductive material has a top width in contact with the dielectric welding layer wider than a bottom width in contact with the barrier layer.

11. The structure of claim 9 , wherein the conductive material is in direct contact with the upper portion of the dielectric welding layer.

12. The structure of claim 9 , wherein a depth is defined between respective top surfaces of the dielectric welding layer and the barrier layer, wherein the depth is from about 15 nm to about 25 nm.

13. The structure of claim 9 , wherein a top surface of the barrier layer is below a top surface of the dielectric welding layer.

14. The structure of claim 9 , wherein the conductive material includes at least one of cobalt, tungsten, copper, aluminum, gold, silver, and alloys thereof.

15. The structure of claim 9 , further comprising:
a silicide region along a bottom of the barrier layer under the conductive material.

16. The structure of claim 9 , wherein the dielectric welding layer is a silicon-containing dielectric material.

17. The structure of claim 16 , wherein the dielectric welding layer is silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, or multilayers thereof.

18. The structure of claim 9 , wherein the barrier layer is titanium nitride, titanium oxide, tantalum nitride, tantalum oxide, or a combination thereof.

19. A structure comprising:
a dielectric layer;
a conductive material formed in the dielectric layer and laterally bound by a barrier layer; and
a dielectric welding layer laterally between the barrier layer and the dielectric layer, wherein the barrier layer and the dielectric welding layer have mismatched heights along a sidewall of the dielectric layer, wherein the mismatched heights define a step height in a range from about 15 nm to about 25 nm.

20. The structure of claim 19 , wherein the dielectric layer and the dielectric welding layer have mismatched heights.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chang Ken-Yu
• Tsai Chun-I
• Tsai Ming-Hsing
• Lin Wei-Jung

Classifications

• H01L21/823475

  Electricity · mapped topic

• H01L21/823418

  Electricity · mapped topic

• H01L21/76846 Primary

  Electricity · mapped topic

• H01L29/66545

  Electricity · mapped topic

• H01L21/67075

  Electricity · mapped topic