Managing high-conflict cache lines in transactional memory computing environments

Patent metadata

Field	Value
Publication number	US-9298626-B2
Application number	US-201314037879-A
Country	US
Kind code	B2
Filing date	Sep 26, 2013
Priority date	Sep 26, 2013
Publication date	Mar 29, 2016
Grant date	Mar 29, 2016

Abstract

Cache lines in a computing environment with transactional memory are configurable with a coherency mode. Cache lines in full-line coherency mode are operated or managed with full-line granularity. Cache lines in sub-line coherency mode are operated or managed as sub-cache line portions of a full cache line. When a transaction accessing a cache line in full-line coherency mode results in a transactional abort, the cache line may be placed in sub-line coherency mode if the cache line is a high-conflict cache line. The cache line may be associated with a counter in a conflict address detection table that is incremented whenever a transaction conflict is detected for the cache line. The cache line may be a high-conflict cache line when the counter satisfies a high-conflict criterion, such as reaching a threshold value. The cache line may be returned to full-line coherency mode when a reset criterion is satisfied.

First claim

What is claimed is:

1. A method for reducing transaction conflicts in a computing environment with transactional memory, the computing environment including a cache configured to hold a plurality of cache lines, each cache line configurable with a coherency mode, the method comprising:
executing a first transaction in the computing environment, the first transaction including a group of instructions operating atomically on a data structure in said memory and accessing a first cache line in a full-line coherency mode, wherein cache control logic associated with the cache is configured to operate or manage the first cache line in the full-line coherency mode that enforces transactional semantics using a full cache line as a granularity of memory accesses to detect transaction conflicts;
detecting a conflicting access of the first cache line while executing the first transaction, the conflicting access resulting in a transactional abort;
based on the detecting, determining that the first cache line is a high-conflict cache line involved in a high number of transaction conflicts, and placing the determined high-conflict first cache line in a sub-line coherency mode, wherein the cache control logic is configured to operate or manage a plurality of sub-cache line portions of the first cache line in the sub-line coherency mode; and
executing a subsequent transaction including a group of instructions operating atomically on the data structure in said memory in the computing environment, the subsequent transaction accessing and managing only a relevant sub-cache line portion of the first cache line in the sub-line coherency mode.

2. The method of claim 1 , further comprising:
receiving, from another requestor in the computing environment, a request for the first cache line in the sub-line coherency mode, the request targeting a memory address within the first cache line;
selecting a first sub-cache line portion of the first cache line, the first sub-cache line portion associated with the memory address;
notifying the requestor that only a sub-cache line portion of the first cache line will be returned; and
returning to the requestor the first sub-cache line portion in response to the request.

3. The method of claim 1 , wherein the first cache line is a first-cache copy of the first cache line in a first cache, and wherein a second-cache copy of the first cache line in a second cache remains in the full-line coherency mode after the placing the first-cache copy in the sub-line coherency mode.

4. The method of claim 1 , further comprising:
marking, while executing the first transaction, a full cache line of the first cache line as transactionally accessed; and
marking, while executing the subsequent transaction, only the relevant sub-cache line portion of the first cache line as transactionally accessed.

5. The method of claim 1 , further comprising:
based on the detecting, incrementing a counter in an entry in a conflict address detection table, the entry associating the counter with the first cache line, wherein the determining that the first cache line is the high-conflict cache line comprises determining that the incremented counter satisfies a high-conflict criterion.

6. A computer system for reducing transaction conflicts in a computing environment with transactional memory, the computing environment including a cache configured to hold a plurality of cache lines, each cache line configurable with a coherency mode, the computer system comprising:
a memory; and
a processor in communication with the memory, wherein the computer system is configured to perform a method, the method comprising:
executing a first transaction in the computing environment, the first transaction including a group of instructions operating atomically on a data structure in said memory and accessing a first cache line in a full-line coherency mode, wherein cache control logic associated with the cache is configured to operate or manage the first cache line in the full-line coherency mode that enforces transactional semantics using a full cache line as a granularity of memory accesses to detect transaction conflicts;
detecting a conflicting access of the first cache line while executing the first transaction, the conflicting access resulting in a transactional abort;
based on the detecting, determining that the first cache line is a high-conflict cache line involved in a high number of transaction conflicts, and placing the determined high-conflict first cache line in a sub-line coherency mode, wherein the cache control logic is configured to operate or manage a plurality of sub-cache line portions of the first cache line in the sub-line coherency mode; and
executing a subsequent transaction including a group of instructions operating atomically on the data structure in said memory in the computing environment, the subsequent transaction accessing and managing only a relevant sub-cache line portion of the first cache line in the sub-line coherency mode.

7. The system of claim 6 , wherein the method further comprises:
based on the detecting, incrementing a counter in an entry in a conflict address detection table, the entry associating the counter with the first cache line, wherein the determining that the first cache line is the high-conflict cache line comprises determining that the incremented counter satisfies a high-conflict criterion.

8. The system of claim 7 , wherein the determining that the incremented counter satisfies the high-conflict criterion comprises:
determining that the incremented counter has reached a threshold value.

9. The system of claim 7 , wherein the determining that the incremented counter satisfies the high-conflict criterion comprises:
calculating a percentage, the percentage based on the incremented counter and a total number of conflicting accesses in the computing environment; and
determining that the percentage has reached a threshold value.

10. The system of claim 7 , wherein the method further comprises:
determining that a reset criterion associated with the counter is satisfied;
resetting the counter based on the determining that the reset criterion is satisfied; and
placing the first cache line in the full-line coherency mode based on the determining that the reset criterion is satisfied.

11. The system of claim 10 , wherein the reset criterion is selected from the group consisting of:
a period of time elapses;
a number of transactions complete;
a number of instructions complete; and
a cache line associated with the counter is cast out of the cache.

12. The system of claim 7 , wherein the entry further associates the counter with at least one cache line adjacent to the first cache line.

13. The system of claim 7 , wherein the entry further associates the counter with a hash value of a memory address associated with the first cache line.

14. A computer program product for reducing transaction conflicts in a computing environment with transactional memory, the computing environment including a cache configured to hold a plurality of cache lines, each cache line configurable with a coherency mode, the computer program product comprising:
a non-transitory computer readable storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method, the method comprising:
executing a first transaction in the computing environment, the first transaction including a group of instructions operating atomically on a data structure in said memory and accessing a first cache line in a full-line coherency mode, wherein cache control logic associated wi

Assignees

• Globalfoundries Inc

Inventors

• Busaba Fadi Y
• Cain Iii Harold W
• Gschwind Michael K
• Michael Maged M
• Salapura Valentina
• Schwarz Eric M
• Shum Chung-Lung K

Classifications

• G06F12/0831 Primary

  using a bus scheme, e.g. with bus monitoring or watching means · CPC title

• G06F9/3004

  to perform operations on memory · CPC title

• G06F9/30087

  Synchronisation or serialisation instructions · CPC title

• G06F12/0828 Primary

  with concurrent directory accessing, i.e. handling multiple concurrent coherency transactions · CPC title