Virtualizing hardware processing resources in a processor

Patent metadata

Field	Value
Publication number	US-12449473-B2
Application number	US-202217691759-A
Country	US
Kind code	B2
Filing date	Mar 10, 2022
Priority date	Mar 10, 2022
Publication date	Oct 21, 2025
Grant date	Oct 21, 2025

Abstract

Processing hardware of a processor is virtualized to provide a façade between a consistent programming interface and specific hardware instances. Hardware processor components can be permanently or temporarily disabled when not needed to support the consistent programming interface and/or to balance hardware processing across a hardware arrangement such as an integrated circuit. Executing software can be migrated from one hardware arrangement to another without need to reset the hardware.

First claim

The invention claimed is:

1. A process for testing integrated circuits comprising:
determining whether hardware processors of an integrated circuit are defective;
based on the determining, modifying the integrated circuit to selectively make hardware processors of the integrated circuit inaccessible; and
based on the determining and the modifying, programming the integrated circuit to designate non-defective hardware processors with virtual identifiers, including classifying, based on the determining, the integrated circuit in accordance with a Skyline representing a population of integrated circuits to be included in a product designator, wherein the Skyline includes (a) a declared quantity of virtual processing clusters, and (b) a declared quantity of processors for each declared virtual processing cluster, wherein different virtual processing clusters declared for the same processor, processing chip or other processing arrangement may have the same or different declared quantities of processors, wherein the Skyline is a representation declaring processing capabilities of the integrated circuit.

2. The process of claim 1 wherein determining comprises testing the integrated circuit for defects.

3. The process of claim 1 wherein modifying includes making functional hardware processors inaccessible based on the classifying.

4. The process of claim 1 wherein the programming includes programming a work distributor within the integrated circuit to provide a façade of virtual identifiers that hides determined defects to thereby present a consistent and uniform work distribution interface across a population of integrated circuits which differ in technological capabilities.

5. The process of claim 1 further including determining a degree of balance of non-defective hardware processors across the integrated circuit and the programming selectively makes hardware processors inaccessible based on the determined degree.

6. The process of claim 5 further including culling the integrated circuit based on the determined degree of balance.

7. A process for testing integrated circuits comprising:
determining whether hardware processors of an integrated circuit are defective;
based on the determining, designating non-defective hardware processors that can serve as Singletons;
classifying, based on the determining, the integrated circuit in accordance with a Skyline representing a population of integrated circuits to be included in a product designator, wherein the Skyline includes (a) a declared quantity of virtual processing clusters, and (b) a declared quantity of processors for each declared virtual processing cluster, wherein different virtual processing clusters declared for the same processor, processing chip or other processing arrangement may have the same or different declared quantities of processors; and
selectively programming the integrated circuit to use the designated non-defective hardware processors as Singletons or instead for use together with other non-defective hardware processors on the integrated circuit to match processing capabilities across the Skyline representing the population of integrated circuits to be included in the product designator.

8. The process of claim 7 wherein the determining comprises testing the integrated circuit for defects.

9. The process of claim 7 wherein modifying includes making functional hardware processors inaccessible based on the classifying.

10. The process of claim 7 wherein the programming includes programming a work distributor within the integrated circuit to provide a façade of virtual identifiers that hides determined defects to thereby present a consistent and uniform work distribution interface across a population of integrated circuits which differ in technological capabilities.

11. The process of claim 7 wherein the determining further includes determining a degree of balance of non-defective hardware processors across the integrated circuit and the programming makes hardware processors inaccessible based on the determined degree.

12. The process of claim 11 further including culling the integrated circuit based on the determined degree.

Assignees

• Nvidia Corp

Inventors

• Duluk Jr Jerome F
• Hirota Gentaro
• Krashinsky Ronny
• Palmer Greg
• Tuckey Jeff
• Nadadhur Kaushik
• Johnson Philip Browning
• Joginipally Praveen

Classifications

• G06F11/07

  Responding to the occurrence of a fault, e.g. fault tolerance · CPC title

• G06F9/50

  Allocation of resources, e.g. of the central processing unit [CPU] · CPC title

• G06F9/48

  Program initiating; Program switching, e.g. by interrupt · CPC title

• G06F9/46

  Multiprogramming arrangements · CPC title

• G01R31/2889

  Interfaces, e.g. between probe and tester (G01R31/31905 and G01R1/07364 take precedence) · CPC title