Integrated circuits with in-field diagnostic and repair capabilities

Patent metadata

Field	Value
Publication number	US-11281195-B2
Application number	US-201715720539-A
Country	US
Kind code	B2
Filing date	Sep 29, 2017
Priority date	Sep 29, 2017
Publication date	Mar 22, 2022
Grant date	Mar 22, 2022

Abstract

An integrated circuit may include an embedded test processor that is capable of performing in-field testing and repair of hardware-related defects without having to remove the integrated circuit from the customer's board. The test processor can be used to drive and monitor test vectors to performing defect screening on input-output circuitry, logic circuitry including lookup table (LUT) circuits and digital signal processing (DSP) circuits, transceiver circuitry, and configuration random-access memory circuitry. The test processor can generate a failure mechanism report and selectively fix repairable defects via a hardware redundancy scheme. The failure mechanism report allows the customer to identify the root cause of failure in the overall system.

First claim

What is claimed is:

1. An integrated circuit, comprising:
programmable logic circuitry; and
a test processor configured to perform in-field testing to detect a hardware defect in the programmable logic circuitry and to determine whether the detected hardware defect in the programmable logic circuitry is capable of being repaired,
wherein the test processor determines a type of the hardware defect in the programmable logic circuitry, and wherein the test processor determines if the type of the hardware defect is electrical overstress or a fabrication defect.

2. The integrated circuit of claim 1 , wherein the test processor sources test vectors for testing the programmable logic circuitry without receiving test signals from an external test host.

3. The integrated circuit of claim 1 , wherein the test processor is further configured to selectively repair the detected hardware defect in the programmable logic circuitry by disabling and bypassing a block that includes the defect while engaging a redundant block that is previously unused.

4. The integrated circuit of claim 1 , wherein the test processor repairs the detected hardware defect by bypassing a defective component and switching into use a redundant component.

5. The integrated circuit of claim 1 , wherein the test processor repairs the detected hardware defect via a software redundancy scheme.

6. The integrated circuit of claim 1 , wherein the test processor determines if the type of the hardware defect that is detected is delamination of a layer of the integrated circuit, a package-level defect, a factory error, or a software error.

7. The integrated circuit of claim 1 , wherein the test processor is further configured to perform in-field testing to detect a hardware defect in input-output circuitry.

8. The integrated circuit of claim 1 , wherein the programmable logic circuitry includes lookup table circuits and digital signal processing circuits.

9. The integrated circuit of claim 1 , wherein the test processor is further configured to perform in-field testing to detect a hardware defect in configuration memory.

10. The integrated circuit of claim 1 , wherein the test processor is further configured to perform in-field testing to detect a hardware defect in transceiver circuitry.

11. A method of testing an integrated circuit, the method comprising:
with a test processor, performing in-field testing to detect a hardware defect in programmable logic circuitry within the integrated circuit; and
with the test processor, determining the type of the hardware defect in the programmable logic circuitry, wherein the test processor determines if the type of the hardware defect is a factory error, a software error, or electrical overstress.

12. The method of claim 11 , further comprising:
in response to detecting the hardware defect within the integrated circuit, selectively repairing the detected hardware defect in the programmable logic circuitry by engaging a hardware redundancy mechanism to bypass the detected hardware defect in the programmable logic circuitry in response to determining that the type of hardware defect is repairable.

13. The method of claim 11 , further comprising:
in response to detecting the hardware defect within the integrated circuit, selectively repairing the detected hardware defect in the programmable logic circuitry by engaging a software redundancy mechanism to restore system-level functionality by loading a new configuration file onto the integrated circuit.

14. The method of claim 11 , further comprising:
asserting a self-diagnostic failure flag in response to determining that the type of the hardware defect is unrepairable.

15. The method of claim 11 , wherein the test processor is either formed on the integrated circuit or external to the integrated circuit.

16. A non-transitory computer-readable storage medium comprising instructions for:
detecting a hardware defect on an integrated circuit die;
determining if a type of the hardware defect is a defect in input-output circuitry, logic circuitry, or memory circuitry on the integrated circuit die; and
generating a failure mechanism report listing the type of the hardware defect that is detected.

17. The non-transitory computer-readable storage medium of claim 16 , wherein the instructions for detecting the hardware defect comprise instructions for:
directing an embedded test processor on the integrated circuit die to screen for hardware faults on the integrated circuit die; and
selectively repairing the hardware faults.

18. The non-transitory computer-readable storage medium of claim 17 , wherein the instructions for directing the embedded test processor to screen for the hardware faults comprise instructions for directing the embedded test processor to screen for hardware faults associated with the input-output circuitry, the logic circuitry, and the memory circuitry on the integrated circuit die.

19. The non-transitory computer-readable storage medium of claim 17 , wherein the instructions for directing the embedded test processor to screen for hardware faults comprise instructions for creating and monitoring test vectors on the integrated circuit die.

20. The non-transitory computer-readable storage medium of claim 17 , wherein the instructions for selectively repairing the hardware faults comprise instructions for:
determining whether the hardware faults are repairable;
bypassing defective components while switching into use redundant components in response to determining that the hardware faults are repairable; and
outputting an error alert in response to determining that the hardware faults are unrepairable.

Assignees

• Intel Corp

Inventors

• Daxer Kenneth T
• Steinke Gregory
• Wright Adam J
• Kantipudi Kalyana Ravindra

Classifications

• H03K19/17764 Primary

  for reliability · CPC title

• G05B19/41875 Primary

  characterised by quality surveillance of production · CPC title

• G05B19/41805

  characterised by assembly · CPC title