Amplification circuit

Patent metadata

Field	Value
Publication number	US-12445095-B2
Application number	US-202217804914-A
Country	US
Kind code	B2
Filing date	Jun 1, 2022
Priority date	Dec 10, 2019
Publication date	Oct 14, 2025
Grant date	Oct 14, 2025

Abstract

An amplification circuit includes a first amplifier provided between an input terminal and an output terminal and a second amplifier connected in parallel with the first amplifier between the input terminal and the output terminal. The first amplifier includes a transistor and a transistor, which are cascode connected with each other. The second amplifier includes a transistor. The transistor has a gate connected to the input terminal, a source connected to ground, and a drain. The transistor has a gate, a source connected to the drain of the transistor, and a drain connected to the output terminal. The transistor has a gate connected to the input terminal, a source connected to ground, and a drain connected to the output terminal.

First claim

The invention claimed is:

1. An amplification circuit comprising:
a first amplifier connected between an input terminal to which a radio-frequency signal is input and an output terminal from which a radio-frequency signal is output; and
a second amplifier connected in parallel with the first amplifier between the input terminal and the output terminal,
wherein the first amplifier comprises a first transistor and a second transistor that are cascode connected with each other,
wherein the second amplifier comprises a third transistor,
wherein the first transistor has a first terminal that is a gate or base connected to the input terminal, a second terminal that is a source or emitter connected to ground, and a third terminal that is a drain or collector,
wherein the second transistor has a fourth terminal that is a gate or base, a fifth terminal that is a source or emitter connected to the third terminal, and a sixth terminal that is a drain or collector connected to the output terminal,
wherein the third transistor has a seventh terminal that is a gate or base connected to the input terminal, an eighth terminal that is a source or emitter connected to ground, and a ninth terminal that is a drain or collector connected to the output terminal,
wherein the amplification circuit is configured to selectively switch between amplification of a radio-frequency signal input to the input terminal using the first amplifier and amplification of the radio-frequency signal input to the input terminal using the second amplifier,
wherein a bias supplied to the first terminal and a bias supplied to the seventh terminal are different from each other, and
wherein a bias supplied to the fourth terminal and a bias supplied to the seventh terminal are different from each other.

2. The amplification circuit according to claim 1 ,
wherein when biases are supplied to the first terminal and the fourth terminal, a bias is not supplied to the seventh terminal, and
wherein when biases are not supplied to the first terminal and the fourth terminal, a bias is supplied to the seventh terminal.

3. The amplification circuit according to claim 1 , further comprising:
a first switch that is connected to a first path, the first path connecting a first connection point and a second connection point to each other via the first amplifier, the first connection point being on an input side of the parallel connection of the first and second amplifiers, and the second connection point being on an output side of the parallel connection of the first and second amplifiers; and
a second switch that is connected to a second path, the second path connecting the first connection point and the second connection point to each other via the second amplifier,
wherein the second switch is in an electrically non-conductive state when the first switch is in an electrically conductive state, and
wherein the second switch is in an electrically conductive state when the first switch is in an electrically non-conductive state.

4. The amplification circuit according to claim 3 ,
wherein the first switch is connected to the first path between the first connection point and the first amplifier, and
wherein the second switch is connected to the second path between the first connection point and the second amplifier.

5. The amplification circuit according to claim 1 , further comprising:
a shunt switch connected between ground and a node between a first connection point and the first amplifier on a first path, or a node between the first connection point and the second amplifier on a second path,
wherein the first path connects the first connection point and a second connection point to each other via the first amplifier, the first connection point being on an input side of the parallel connection of the first and second amplifiers, the second connection point being on an output side of the parallel connection of the first and second amplifiers, and
wherein the second path connects the first connection point and the second connection point to each other via the second amplifier.

6. The amplification circuit according to claim 5 , further comprising:
a first input matching network connected between the input terminal and the first amplifier; and
a second input matching network connected between the input terminal and the second amplifier,
wherein the shunt switch is connected between the first input matching network and the first amplifier or between the second input matching network and the second amplifier.

7. The amplification circuit according to claim 1 , further comprising:
a protection circuit connected between ground and a node between a first connection point and the first amplifier on a first path, or a node between the first connection point and the second amplifier on a second path,
wherein the first path connects the first connection point and a second connection point to each other via the first amplifier, the first connection point being on an input side of the parallel connection of the first and second amplifiers, the second connection point being on an output side of the parallel connection of the first and second amplifiers, and
wherein the second path connects the first connection point and the second connection point to each other via the second amplifier.

8. The amplification circuit according to claim 1 ,
wherein a series switch is not in a first path or a second path,
wherein the first path connects a first connection point and a second connection point to each other via the first amplifier, the first connection point being on an input side of the parallel connection of the first and second amplifiers, and the second connection point being on an output side of the parallel connection of the first and second amplifiers, and
wherein the second path connects the first connection point and the second connection point to each other via the second amplifier.

9. The amplification circuit according to claim 1 , further comprising:
a bypass path that is connected between the input terminal and the output terminal in parallel with a main path in which the first amplifier and the second amplifier are connected in parallel with each other.

10. The amplification circuit according to claim 9 , further comprising:
a series switch in the main path at least between a first connection point and a third connection point, or between a second connection point and a fourth connection point,
wherein the first connection point is on an input side of the parallel connection of the first and second amplifiers, and the third connection point is on an input side of the parallel connection of the main and bypass paths, and
wherein the second connection point is on an output side of the parallel connection of the first and second amplifiers, and the fourth connection point is on an output side of the parallel connection of the main and bypass paths.

11. The amplification circuit according to claim 10 , further comprising:
an input matching network connected between the first connection point and the third connection point,
wherein the series switch is connected between the input matching network and the first connection point.

12. The amplification circuit according to claim 10 , further comprising:
an input matching network connected between the first connection point and the third connection point,
wherein the series switch is connected between the input matching network and the third connection point.

13. The amplification circuit according to claim 1 , further comprising:
a first input matching network connected between the input terminal and the first amplifier; and

Assignees

• Murata Manufacturing Co

Inventors

• Sugiyama Koudai

Classifications

• H03F3/191

  Tuned amplifiers (H03F3/193, H03F3/195 take precedence) · CPC title

• H03F1/0277

  Selecting one or more amplifiers from a plurality of amplifiers · CPC title

• H03F1/223 Primary

  with MOSFET's · CPC title

• H03G2201/307

  being radio frequency signal · CPC title

• H03G2201/103

  being an amplifying element · CPC title