Circuits and methods for reducing supply sensitivity in a power amplifier

Patent metadata

Field	Value
Publication number	US-2016112018-A1
Application number	US-201414518967-A
Country	US
Kind code	A1
Filing date	Oct 20, 2014
Priority date	Oct 20, 2014
Publication date	Apr 21, 2016
Grant date	—

Abstract

In one embodiment, the present disclosure includes a circuit comprising a first power amplifier stage having an input to receive an input signal, an output coupled to an output node, the first power amplifier stage receiving a time-varying power supply voltage. The circuit further includes a second power amplifier stage configured in parallel with the first power amplifier stage having an input to receive the input signal, an output coupled to the output node, the second power amplifier stage receiving the time-varying power supply voltage. A first gain of the first power amplifier stage decreases when the power supply voltage is in a first low voltage range, and a second gain of the second power amplifier stage compensates for the decreasing gain of the first power amplifier stage in the first low voltage range.

First claim

What is claimed is:

1 . A circuit comprising:
a first power amplifier stage having an input to receive an input signal, an output coupled to an output node, the first power amplifier stage receiving a time-varying power supply voltage; and a second power amplifier stage configured in parallel with the first power amplifier stage having an input to receive the input signal, an output coupled to the output node, the second power amplifier stage receiving the time-varying power supply voltage, wherein a first gain of the first power amplifier stage decreases when the power supply voltage is in a first low voltage range, and wherein a second gain of the second power amplifier stage compensates for the decreasing gain of the first power amplifier stage in the first low voltage range.

2 . The circuit of claim 1 wherein the first power amplifier stage comprises a first transistor, the first transistor having a control terminal coupled to receive the input signal and a first terminal coupled to the power supply voltage through the output node, and wherein the second power amplifier stage comprises a second transistor, the second transistor having a control terminal coupled to receive the input signal and a first terminal coupled to the power supply voltage through one or more stacked transistors and the output node.

3 . The circuit of claim 2 wherein the first transistor is first device type and the second transistor is a second device type.

4 . The circuit of claim 2 wherein the first transistor and the second transistor are coupled to different gate bias voltages.

5 . The circuit of claim 2 wherein the first transistor and the second transistor are coupled to the same gate bias voltage.

6 . The circuit of claim 2 wherein the one or more stacked transistors are two transistors configured in cascode.

7 . The circuit of claim 2 wherein the second transistor comprises a plurality of segments, and wherein a different number of segments are activated based on the power supply voltage.

8 . The circuit of claim 7 wherein the one or more of the segments comprise:
a source, a gate, and drain;
a first switch coupled between the gate and a reference voltage; and
a second switch coupled to the gate.

9 . The circuit of claim 8 wherein the drains of the segments are coupled together, the sources of the segments are coupled together, and wherein when a segment is activated the first switch on a particular segment is opened and the second switch is closed to turn on the particular segment, and wherein when the segment is not activated the first switch is closed and the second switch is opened to turn off the particular segment.

10 . The circuit of claim 1 wherein the first power amplifier stage comprises a first high voltage transistor, the first high voltage transistor having a control terminal coupled to receive the input signal and a first terminal coupled to the power supply voltage through the output node, and wherein the second power amplifier stage comprises a second standard transistor, the second standard transistor having a control terminal coupled to receive the input signal and a first terminal coupled to the power supply voltage through at least one high voltage transistor and the output node.

11 . A method comprising:
receiving an input signal in a first power amplifier stage, and in accordance therewith, producing an output signal on an output node, the first power amplifier stage receiving a time-varying power supply voltage; and receiving the input signal in a second power amplifier stage configured in parallel with the first power amplifier stage, and in accordance therewith, producing the output signal on the output node, the second power amplifier stage receiving the time-varying power supply voltage, wherein a first gain of the first power amplifier stage decreases when the power supply voltage is in a first low voltage range, and wherein a second gain of the second power amplifier stage compensates for the decreasing gain of the first power amplifier stage in the first low voltage range.

12 . The method of claim 11 wherein the first power amplifier stage comprises a first transistor, the method further comprising receiving the input signal on a control terminal of the first transistor, wherein a first terminal of the first transistor is coupled to the power supply voltage through the output node, and wherein the second power amplifier stage comprises a second transistor, the method further comprising receiving the input signal on a control terminal of the second transistor, wherein a first terminal of the second transistor is coupled to the power supply voltage through one or more stacked transistors and the output node.

13 . The method of claim 12 wherein the first transistor is first device type and the second transistor is a second device type.

14 . The method of claim 12 wherein the first transistor is high voltage MOS device, the one or more cascode transistors are high voltage MOS devices, and the second transistor is not a high voltage MOS device.

15 . The method of claim 12 wherein the first transistor and the second transistor are coupled to different gate bias voltages.

16 . The method of claim 12 wherein the first transistor and the second transistor are coupled to the same gate bias voltage.

17 . The method of claim 12 wherein the second transistor comprises a plurality of segments, the method further comprising activating a different number of segments based on the power supply voltage.

18 . The method of claim 17 wherein the one or more of the segments comprise:
a source, a gate, and drain;
a first switch coupled between the gate and a reference voltage; and
a second switch coupled to the gate.

19 . The method of claim 18 wherein the drains of the segments are coupled together, the sources of the segments are coupled together, and wherein when a segment is activated the first switch on a particular segment is opened and the second switch is closed to turn on the particular segment, and wherein when the segment is not activated the first switch is closed and the second switch is opened to turn off the particular segment.

20 . A circuit comprising:
first power amplifier means having an input to receive an input signal, an output coupled to an output node, the first power amplifier stage receiving a time-varying power supply voltage; and second power amplifier means configured in parallel with the first power amplifier means having an input to receive the input signal, an output coupled to the output node, the second power amplifier stage receiving the time-varying power supply voltage, wherein a first gain of the first power amplifier means decreases when the power supply voltage is in a first low voltage range, and wherein a second gain of the second power amplifier means compensates for the decreasing gain of the first power amplifier means in the first low voltage range.

Assignees

• Qualcomm Inc

Inventors

• Scuderi Antonino
• Hadjichristos Aristotele

Classifications

• H03F1/56

  Modifications of input or output impedances, not otherwise provided for · CPC title

• H03F3/19 Primary

  with semiconductor devices only · CPC title

• H03F2203/21106

  An input signal being distributed in parallel over the inputs of a plurality of power amplifiers · CPC title

• H03F3/211 Primary

  using a combination of several amplifiers (H03F3/60 takes precedence) · CPC title

• H03F2200/451

  the amplifier being a radio frequency amplifier · CPC title