Radio frequency (RF) amplifier

Patent metadata

Field	Value
Publication number	US-10141894-B1
Application number	US-201715640659-A
Country	US
Kind code	B1
Filing date	Jul 3, 2017
Priority date	Jul 3, 2017
Publication date	Nov 27, 2018
Grant date	Nov 27, 2018

Abstract

A circuit includes a first amplifier path comprising a first amplifier, MA, a second amplifier path comprising a cascode device and a second amplifier, MB, a node defined by a source of the cascode device and a drain of the second amplifier, MB, and a capacitance coupled between the node and a source of the second amplifier, MB.

First claim

What is claimed is:

1. A circuit, comprising:
a first amplifier path comprising a first amplifier, M A ;
a second amplifier path comprising a cascode device and a second amplifier, M B ;
a node defined by a source of the cascode device and a drain of the second amplifier, M B ;
a capacitance coupled between the node and a source of the second amplifier, M B ; and
an input configured to receive a radio frequency signal, the input being coupled to a gate of the first amplifier, M A , and to a gate of the second amplifier, M B .

2. The circuit of claim 1 , wherein:
the first amplifier path is configured to carry a first current, I A ;
the second amplifier path is configured to carry a second current, I B ; and
the capacitance is configured to create a phase displacement between the second current, I B , and the first current, I A .

3. The circuit of claim 2 , wherein the phase displacement between the second current, I B , and the first current, I A reduces a third order intermodulation (IM3) component in an output of the first amplifier, M A , and the second amplifier, M B .

4. The circuit of claim 2 , wherein the phase displacement between the second current, I B , and the first current, I A comprises a phase lag in the second current, I B , with respect to the first current, I A .

5. The circuit of claim 1 , wherein the capacitance is programmable over a range of frequencies and a range of gain states.

6. The circuit of claim 1 , wherein a value of the capacitance is between zero and one picofarad (pF).

7. The circuit of claim 1 , further comprising:
an additional cascode device located in the first amplifier path such that the first amplifier path and the second amplifier path each comprise a cascode amplifier arrangement.

8. The circuit of claim 1 , wherein the circuit is single-ended.

9. The circuit of claim 1 , wherein the circuit is differential.

10. The circuit of claim 1 , wherein the capacitance further comprises a switchable capacitor.

11. The circuit of claim 10 , wherein the switchable capacitor comprises a capacitor bank having a plurality of switchable capacitors.

12. A circuit, comprising:
means for providing adjustable capacitance at a cascode node of an amplifier, the amplifier having a first amplifier path comprising a first amplifier, M A and a second amplifier path comprising a cascode device and a second amplifier, M B ;
means for adjusting the capacitance at the cascode node to minimize third order intermodulation distortion (IMD3) in the amplifier; and
input means for receiving a radio frequency signal, the input means being coupled to a gate of the first amplifier, M A , and to a gate of the second amplifier, M B .

13. The circuit of claim 12 , further comprising:
means for conducting a first current, I A , in a first amplification path; and
means for conducting a second current, I B , in a second amplification path, wherein the means for adjusting the capacitance to minimize third order intermodulation distortion (IMD3) in the amplifier creates a phase displacement between the second current, I B , and the first current, I A .

14. The circuit of claim 13 , wherein the means for adjusting the capacitance creates a phase lag in the second current, I B , with respect to the first current, I A .

15. The circuit of claim 12 , wherein the means for adjusting the capacitance comprises switchable capacitance means.

16. A method for an amplifier, comprising:
amplifying a signal in a first amplifier path carrying a first current, I A ;
amplifying the signal in a second amplifier path carrying a second current, I B ;
adjusting a capacitance at a cascode node of the second amplifier path to reduce third order intermodulation distortion (IMD3) in the amplifier; and
providing a radio frequency signal to an input, the input being coupled to a gate of a first amplifier, M A , in the first amplifier path and to a gate of a second amplifier, M B in the second amplifier path.

17. The method of claim 16 , wherein adjusting the capacitance to reduce third order intermodulation distortion (IMD3) in the amplifier comprises creating a phase displacement between the second current, I B , and the first current, I A .

18. The method of claim 17 , wherein the phase displacement between the second current, I B , and the first current, I A comprises a phase lag in the second current, I B , with respect to the first current, I A .

19. The method of claim 16 , wherein the capacitance is programmable over a range of frequencies and a range of gain states.

20. The method of claim 16 , further comprising adjusting a value of the capacitance between zero and one picofarad (pF).

21. The method of claim 16 , further comprising adjusting a value of the capacitance using a switchable capacitor.

22. An amplifier, comprising:
a first amplifier path comprising a first cascode device and a first amplifier, M A , the first amplifier path configured to carry a first current, I A ;
a second amplifier path comprising a second cascode device and a second amplifier, M B , the second amplifier path configured to carry a second current, I B ; and
a capacitor coupled between a source of the second amplifier, M B , and a node disposed between a source of the second cascode device and a drain of the second amplifier, M B , the capacitor configured to create a phase displacement between the second current, I B , and the first current, I A .

23. The amplifier of claim 22 , wherein the phase displacement between the second current, I B , and the first current, I A reduces a third order intermodulation (IM3) component in an output of the amplifier.

24. The amplifier of claim 22 , wherein the phase displacement between the second current, I B , and the first current, I A comprises a phase lag in the second current, I B , with respect to the first current, I A .

25. The amplifier of claim 22 , wherein the capacitor is programmable over a range of frequencies and a range of gain states.

26. The amplifier of claim 22 , wherein a value of the capacitance is between zero and one picofarad (pF).

27. The amplifier of claim 22 , wherein the amplifier is configured to receive an input signal at an input node and provide an output signal at an output node, the input node being coupled to a gate of the first amplifier, M A , via a second capacitor and to a gate of the second amplifier, M B , via a third capacitor, and the output node being coupled to a drain of the first cascode device and to a drain of the second cascode device.

28. The amplifier of claim 22 , wherein the capacitor comprises a switchable capacitor.

29. The amplifier of claim 28 , wherein the switchable capacitor comprises a capacitor bank having a plurality of switchable capacitors.

30. A circuit, comprising:
a first amplifier path comprising a first amplifier, M A ;
a second amplifier path comprising a cascode device and a second amplifier, M B ;
a node defined by a source of the cascode device and a drain of the second amplifier, M B ; and
a capacitance coupled between the node and a source of the second amplifier, M B , the capacitance comprising a switchable capacitor.

Assignees

• Qualcomm Inc

Inventors

• Aruppukottai Boominathan Karthikeya
• Thiagarajan Krishnaswamy
• Ranjan Mahim

Classifications

• H03F1/3205 Primary

  in field-effect transistor amplifiers · CPC title

• H03F2200/294

  the amplifier being a low noise amplifier [LNA] · CPC title

• H03F1/223

  with MOSFET's · CPC title

• H03F2200/451

  the amplifier being a radio frequency amplifier · CPC title

• H03F3/195

  in integrated circuits · CPC title