Heterogeneous bonding for photonic integration

Patent metadata

Field	Value
Publication number	US-12444723-B2
Application number	US-202217949022-A
Country	US
Kind code	B2
Filing date	Sep 20, 2022
Priority date	Oct 13, 2009
Publication date	Oct 14, 2025
Grant date	Oct 14, 2025

Abstract

A method of fabricating a composite integrated optical device includes providing a substrate comprising a silicon layer, forming a waveguide in the silicon layer, and forming a layer comprising a metal material coupled to the silicon layer. The method also includes providing an optical detector, forming a metal-assisted bond between the metal material and a first portion of the optical detector, forming a direct semiconductor-semiconductor bond between the waveguide, and a second portion of the optical detector.

First claim

What is claimed is:

1. A method of forming an integrated optical device, comprising:
providing a substrate that forms:
an upper substrate surface, and
a recess within the upper substrate surface, the recess forming a lower substrate surface, the lower substrate surface and the upper substrate surface defining a recess height therebetween, and wherein one or more first metal pads are deposited on to the lower substrate surface within the recess;

providing a compound semiconductor device comprising an upper device surface and a lower device surface, wherein:
the upper device surface and the lower device surface define a device height therebetween, and
one or more second metal pads are deposited on to the lower device surface;

bonding the one or more first metal pads to respective ones of the one or more second metal pads, with respective portions of a bonding metal, wherein the bonding metal comprises In x Pd y ; and
depositing a planarizing material that fills at least a portion of the recess.

2. The method of claim 1 , wherein the bonding metal comprises In 0.7 Pd 0.3 as the bonding metal.

3. The method of claim 1 , wherein:
the substrate comprises a waveguide;
the compound semiconductor device is configured to emit light; and
the compound semiconductor device and the substrate are arranged to couple the light emitted by the compound semiconductor device into the waveguide.

4. The method of claim 1 , wherein:
the device height exceeds the recess height, and
after the bonding, and before subsequent processing, a height of the upper device surface of the compound semiconductor device exceeds a height of the upper substrate surface.

5. The method of claim 1 , wherein:
the substrate comprises a waveguide;
the compound semiconductor device is configured to emit light; and
the compound semiconductor device and the substrate are arranged to couple the light emitted by the compound semiconductor device into the waveguide.

6. The method of claim 1 , wherein the substrate comprises a silicon waveguide.

7. The method of claim 1 , wherein depositing the planarizing material comprises:
depositing the planarizing material to a height that exceeds a height of an uppermost surface of the compound semiconductor device; and
covering the uppermost surface of the compound semiconductor device with the planarizing material.

8. The method of claim 7 , furthermore comprising:
forming one or more openings through the planarizing material; and
forming interconnect metal to couple with the uppermost surface of the compound semiconductor device through the one or more openings.

9. The method of claim 8 , wherein forming the interconnect metal comprises forming at least one portion of the interconnect metal that connects an uppermost substrate surface with the compound semiconductor device, through respective ones of the one or more openings.

10. The method of claim 1 , wherein bonding the one or more first metal pads to the respective ones of the one or more second metal pads comprises providing In x Pd y as the bonding metal.

11. The method of claim 1 , wherein the one or more first metal pads or the one or more second metal pads comprise at least one of Ti, Cr, Pt, Ni or W.

12. The method of claim 1 , wherein the compound semiconductor device is configured to emit light.

13. The method of claim 1 , wherein:
the compound semiconductor device has a lowermost surface, which is lower than the lower device surface; and
the substrate and the compound semiconductor device form a direct semiconductor/semiconductor contact between the lower substrate surface and the lowermost surface of the compound semiconductor device.

14. The method of claim 1 , wherein the compound semiconductor device is a detector.

15. The method of claim 1 , wherein the substrate is a silicon-on-insulator (SOI) substrate comprising a silicon device layer and a waveguide in the silicon device layer.

16. The method of claim 1 , further comprising thinning the compound semiconductor device to be coplanar with a silicon device layer of the substrate.

Assignees

• Skorpios Tech Inc

Inventors

• Krasulick Stephen B
• Dallesasse John

Classifications

• H10W90/00 Primary

  Package configurations · CPC title

• H10H20/8506

  Containers · CPC title

• H10H20/857

  Interconnections, e.g. lead-frames, bond wires or solder balls · CPC title

• H10H20/84

  Coatings, e.g. passivation layers or antireflective coatings · CPC title

• H10H20/018

  Bonding of wafers · CPC title